Orise Tech Adopts SpyGlass® CDC & Constraints

Measures Best Runtime, Memory Footprint & Ease of Use  

SAN JOSE, Calif. – Sept 4, 2014 – Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced that Orise Technology has adopted Atrenta's SpyGlass CDC (Clock Domain Crossing) and Constraints analysis tool suite to enhance its IC design and verification flow. This addition has helped the team realize a more efficient design workflow which provides high quality and low noise reports of design issues.

“At Orise Tech, we specialize in development of Flat Panel Display drivers and controllers,” said Chia-Yuan Chang, vice president of R&D at Orise technology. “Our customers demand the highest quality ICs with the latest technology on a regular basis. SpyGlass provides an efficient working environment for design analysis and debug, greatly improving our designers’ productivity.”

To meet their critical schedules and quality demands, Orise Tech sought out a robust RTL analysis solution. The primary focus was to detect CDC issues and ensure SDC completeness with easy setup and debug for their engineering teams. A secondary concern was the runtime and memory usage of the solution over their test suite.

The SpyGlass advanced technology, combined with the easy-to-use common interface and extensive dashboard reporting structure provided the ultimate solution for Orise Tech. SpyGlass Lint, CDC and Constraints covered and found more design issues than any other solution. SpyGlass also provided a dashboard report with the highest quality information and the least amount of noise, or irrelevant data. Finally, the runtime was shorter than any other tool while the memory footprint was less, allowing for more runs on their existing computing hardware.

“Atrenta prides itself on a rich multi-domain analysis platform targeted for RTL designers,” said Piyush Sancheti, vice president of marketing at Atrenta. “The combination of our Lint, CDC and Constraints technology in an integrated platform is a perfect example. You must ensure that RTL and SDC are clean going into CDC analysis, and you can do this all in one pass inside SpyGlass. We are thrilled to have Orise Technology adopt our industry leading RTL Signoff solution.”

About Atrenta Inc.

Atrenta's SpyGlass Predictive Analyzer® significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred fifty companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the addition of BugScope™ verification efficiency is also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.

SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com

For more information:

Charu Puri
Email Contact

© 2014 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, SpyGlass Predictive Analyzer, and GenSys are registered trademarks and BugScope is a trademark of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this release.

Review Article Be the first to review this article
DAC 2020

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
D2S Brings GPU Acceleration to Semiconductor Design and Manufacturing
Senior Layout Engineer for EDA Careers at EAST COAST, California
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Software Engineer for EDA Careers at RTP, North Carolina
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Upcoming Events
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise