System-Level Advantages of 3D Integration

SAN JOSE, CA -- (Marketwired) -- Nov 04, 2014 --


Who:
Mike Gianfagna, vice president of marketing at eSilicon, a leading independent semiconductor design and manufacturing solutions provider

What:
Panel discussion: System Level Advantages of 3D Integration

Where:
International Wafer-Level Packaging Conference (IWLPC) 2014, DoubleTree San Jose, Oak Ballroom

When:
November 11, 2014, 1:15-2:45pm

More:
Panelists include Mike Gianfagna, eSilicon; Ramakanth Alapati, GLOBALFOUNDRIES; Bel Haba, Google; Simon McElrea, Invensas Corporation; E. Jan Vardaman, TechSearch International Inc.; Robert Patti, Tezzaron Semiconductor Corp. and Rozalia Beica, Yole Développement. Moderated by Francoise von Trapp, 3D InCites, Inc.

Abstract:
System-level integrators and manufacturers will face off in a discussion about the system-level advantages of 3D IC, whether 3D ICs can solve the issues of SoC design complexity and the cost of CMOS scaling to future nodes

About eSilicon
eSilicon, a leading independent semiconductor design and manufacturing solutions provider, delivers custom ICs and custom IP to OEMs, independent device manufacturers (IDMs), fabless semiconductor companies (FSCs) and wafer foundries through a fast, flexible, lower-risk, automated path to volume production. eSilicon serves a wide variety of markets including communications, computer, consumer, industrial products and medical. www.esilicon.com

eSilicon -- Enabling Your Silicon Success™

eSilicon is a registered trademark, and the eSilicon logo and Enabling Your Silicon Success are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.

Contacts:
Sally Slemons 
eSilicon Corporation 
408.635.6409 

Email Contact

Susan Cain 
Cain Communications 
408.393.4794

Email Contact 





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