ChipPAC Announces Package-in-Package (PiP(TM)) a Novel 3D Package Stacking Technology

PiP(TM) Module Chosen for the Technology Innovation Showcase at SEMICON West

FREMONT, Calif., July 12 /PRNewswire-FirstCall/ -- ChipPAC, Inc. (NASDAQ: CHPC), one of the world's largest and most diversified providers of semiconductor assembly and test services, today announced that it is developing a novel proprietary package-stacking technology PiP (TM) (Package-in-Package) for cell phone applications.

PiP is a 3-D package that stacks a fully tested Internal Stacked Module (ISM) on top of a Base Assembly Package (BAP) and interconnects them with wire bonding and molds into one standard CSP. The ISM is a standard Land Grid Array (LGA) that can stack multiple memory chips like Flash (NOR/NAND), SDRAM and SDR/DDR. The BAP is a standard Ball Grid Array (BGA) which can be a single ASIC chip or a stack of ASIC and Analog or other chips as determined by the application. ChipPAC is developing the first member of this family of packages for a major DSP supplier for cell phone applications. Also in collaboration with the customer and two major memory suppliers ChipPAC is driving the standards for the ISM including physical dimensions, and electrical and mechanical specifications.

PiP will be exhibited at the SEMICON West Technology Innovation Showcase (TIS). It was chosen based on technical merit and relevance to the semiconductor industry. TIS highlights innovative companies, inventors and entrepreneurs.

Dennis McKenna, Chairman and CEO of ChipPAC, Inc., commented, "The 3-D packaging market is exploding with the growth of enhanced phones. Package-in- Package is ideal for cell phone applications because it provides greater functional integration, efficient use of motherboard real estate and an overall reduction in total cost. Die stacking to date has been primarily with memory-to-memory devices. As we look to stack logic and many types of memory, with different wafer-fab sources, processes, and die shrinks, we will face greater manufacturing risks. Package-in-Package reduces these risks. The stacking of pre-tested packages allows for design flexibility, competitive sourcing and shorter time-to-market, with minimum risk versus the alternatives of SOC (System on a Chip) or die stacking. By standardizing the package design, customers will have greater flexibility in sourcing the ASICs and memory devices."

Gartner Dataquest forecasts 3-D stacked packages in cell phones to go from 300M units in 2003 to 800M units in 2007. SiP (System in a Package) is expected to grow at a 55.6% CAGR over the next five years, according to Semico Research. This will be the fastest growth segment in semiconductors.

Customers can integrate an ASIC with a combination of memories in a minimal footprint and low profile CSP typically 15x15 mm at 1.4 mm profile with >500 solder balls at 0.5 mm pitch. A low Non Recurring Expense (NRE) similar to that of a typical package, a low PiP packaging cost and a significantly reduced final test complexity result in a module with lower cost of ownership. The flexibility of combining an ASIC and Memory sourced in the open market provides for a broad choice of applications with short time-to- market and low risk.

"PiP technology utilizes existing package materials, manufacturing equipment and assembly processes and is identical to a standard CSP package in the eyes of the customer" said Marcos Karnezos, Chief Technology Officer of ChipPAC, Inc. "PiP meets the accepted package and board level reliability standards of a CSP with a Moisture Resistance Test (MRT) L2a and is compliant to Lead Free and Green specifications. This allows for a standard board mount and does not require any special handling at the board mounting houses"

About ChipPAC, Inc.

ChipPAC is a full-portfolio provider of semiconductor packaging design, assembly, test and distribution services. The company combines a history of innovation and service with more than a decade of experience satisfying some of the largest customers in the industry. With advanced process technology capabilities and a global manufacturing presence spanning Korea, China, Malaysia and the United States, ChipPAC has a reputation for providing dependable, high quality packaging solutions. For more information, visit the company's Web site at .

   David Pasquale, 646-536-7006, or Moon Lee, 646-536-7001
   Both with The Ruth Group,

  Forward-Looking Statements:

This press release includes forward-looking statements, as that term is defined in the Private Securities Reform Act of 1995, which are subject to known and unknown risks and uncertainties that could cause actual results to differ materially from those expressed or implied by such statements. These forward-looking statements include statements regarding the company's proposed merger with ST Assembly Test Services Ltd ("STATS" - Nasdaq: STTS and SGX: ST Assembly), growth strategy, sales expectations, customers, competition, and visibility. Some of these risks and uncertainties are detailed in documents filed with the Securities and Exchange Commission. The Company undertakes no obligation to update the information in this press release.

CONTACT: David Pasquale, +1-646-536-7006, or Moon Lee, +1-646-536-7001,
both of The Ruth Group, for ChipPAC, Inc.

Web site:

Review Article Be the first to review this article

 Advanced Asembly

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
You’re Invited! SEMI’s Innovation for a Transforming World
intelThe Dominion of Design
by intel
The Long Game: Product and Security Assurance
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Setting a High Standard for Standards-Based IP
Business Operations Planner for Global Foundaries at Santa Clara, California
Test and Measurement System Architect for Xilinx at San Jose, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
Technical Product Manager- SISW-EDA 238452 for Siemens AG at Fremont, California
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
Upcoming Events
Join Chipx2021 - at Tel Aviv Expo convention center Tel Aviv Israel - Jun 21 - 22, 2021
Innovation for a Transforming World -virtual Event at United States - Jul 13 - 14, 2021
DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021
SEMICON Southeast Asia 2021 Hybrid Event at Setia SPICE Convention Centre Penang Malaysia - Aug 23 - 27, 2021
Verific: SystemVerilog & VHDL Parsers

© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise