Atrenta Presents Expanded RTL Signoff Platform at 52nd DAC

Addressing SoC Challenges of Scale, Complexity, and Advanced Nodes

SAN JOSE, Calif. — (BUSINESS WIRE) — June 4, 2015 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced that it will present key new additions to its RTL Signoff platform at the 52nd Design Automation Conference to be held June 7-11, 2015 at Moscone Center in San Francisco, California. Atrenta’s RTL Signoff platform, built on its industry leading SpyGlass®, BugScope® and GenSys® tools, enables efficient verification and optimization of SoCs early in the design cycle, thus minimizing time to design closure and avoiding critical chip failures.

While SoCs are becoming bigger and more complex, the use of advanced process nodes has made RTL Signoff a design imperative. At DAC, Atrenta will showcase how its RTL Signoff platform has been expanded to address these challenges. Some key highlights are:

SpyGlass Platform

  • Next generation, SpyGlass Turbo that is “Smarter, Faster, and Deeper”
  • IP Signoff solution with a broader industry adoption and hooks for SoC integration
  • Seamless Clock Domain Crossing (CDC) flow for FPGA designs
  • Static SoC connectivity verification
  • CDC verification for RTL and netlist including structural, functional and hierarchical methods
  • Reset Domain Crossing (RDC) verification
  • Timing constraint management including equivalence, propagation and timing exception verification
  • An integrated platform for RTL power estimation, optimization, and verification
  • Hard-to-test fault analysis at RTL for manufacturing test

GenSys Platform for chip assembly, surgical RTL generation, and SDC restructuring

BugScope Apps for progressive functional / code coverage tracking, and automatic assertion generation for SoC simulation and emulation

For a complete listing of suite sessions at the Atrenta DAC booth #1732, please visit: http://www.atrenta.com/DAC2015/sessions.php

“It was two years ago at DAC that we launched our RTL Signoff platform, and the response from our 280+ customers has been overwhelmingly positive,” said Piyush Sancheti, vice president of marketing at Atrenta. “We have continued to expand the scope of our RTL platform to address the next set of SoC challenges of scale, complexity, and advanced process nodes. We look forward to sharing our progress with prospects, customers, and partners at DAC.”

In addition to show floor activities, Atrenta will be featured in 11 Designer Track papers and posters, where customers share their experience using Atrenta products to solve critical design challenges. Atrenta will also participate in a Sunday DAC workshop on Enterprise-Level IP Management. For the 7th year in a row, Atrenta, as the founding sponsor for the “ I Love DAC” campaign, has provided users with free access to DAC. Atrenta is also a top sponsor for the “ Stars of IP Party” hosted by IP-Extreme and the “ Love IP Party at DAC” hosted by Heart of Technology. For a complete listing of all Atrenta activities at DAC, please visit: http://www.atrenta.com/DAC2015/

About Atrenta Inc.

Atrenta's SpyGlass Predictive Analyzer® significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred eighty companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. With the addition of GenSys® and BugScope®, RTL modification and verification efficiency are also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.

SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com

© 2015 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, SpyGlass Predictive Analyzer, GenSys and BugScope are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this release.



Contact:

Atrenta:
Danielle Arnold, 408-453-3333
Email Contact




Review Article Be the first to review this article
Aldec

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Modesto (Mo) CasasGlobal Business in EDA
by Modesto (Mo) Casas
The Contingent Purchase Order Reassures Buyer and Seller
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Meet the New Cylynt, Fighting Software Piracy Around the Globe
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Jobs
Senior Physical Design/Layout Engineer for EDA Careers at EAST COAST, California
Digital Design ASIC Manager for EDA Careers at RTP, North Carolina
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Upcoming Events
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020
Drive World Conference & Expo at Santa Clara Convention Center Santa Clara CA - Aug 11 - 13, 2020
Verific: SystemVerilog & VHDL Parsers
TrueCircuits:



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise