Mar 30, 2016 -- The DVCon 2016 panel “ Redefining ESL” was a lively and popular panel, with 135 attending despite the early hour. Moderated by Brian Bailey of Semiconductor Engineering, it featured a variety of views on the role of ESL (“Electronic System Level”) in design and verification for both hardware and software.
Panelists included (from left to right below)
- Patrick Sheridan, Synopsys
- Raik Brinkmann, One Spin
- Simon Davidmann, Imperas Software Ltd.
- Bryan Bowyer, Mentor
- Dave Pursley, Cadence
- Adnan Hamid, Breker
Simon Davidmann of Imperas Software Ltd. kicked off the discussion by questioning the very definition of ESL, calling the terminology a “misnomer” and contending that the key issue is designing electronic products: not just the hardware, but both hardware and software. He stated: “EDA vendors need to move away from selling the technology they’ve got, and focus on solving the developers’ problems.” He emphasized the importance of embedded software: “The things we need to design aren’t just blocks. There is a tremendous amount of software… It’s all about the software!”
Simon believes that we need to evolve all of the different methodologies commonly grouped under ESL to deal with system complexity. Virtual platforms are needed for early software simulation as well as hardware/ software debug, and verification at the system level needs to include running the software stack. He described an example in which one customer needed to simulate 14 trillion instructions to solve a software issue. This can be done with virtual platforms, which are available early in the development flow, while emulation is expensive and only available late in the design cycle. Simon believes that synthesis must move up to a higher level as well. He sees EDA as in the infancy of this evolution, and called for “Electronic Design 3.0” to address these issues.
Dave Pursley of Cadence Design Systems, Inc. took as his position, “Who wouldn’t want a flow from TLM to GDSII?” He recommended adoption of ESL technology and endorsed the value of moving to a higher level of abstraction, saying that debug at the ESL level helps find more significant, and different, bugs than debugging at the RTL level, which often just catches “RTL typos.” He also believes that companies can adopt various technologies for ESL without adding great overhead to the flow.
Bryan Bowyer of Mentor Graphics Corp. agreed that ESL is difficult to define, taking the position “ESL looks fragmented because it means too many things to too many people; let’s focus.” He noted that ESL includes both high-level synthesis (HLS) and the use of virtual platforms, and that there needs to be better links between them. He believes “the next step for the high-level synthesis segment of ESL is to standardize on a synthesis subset and integrate the same verification methodology found in modern RTL design and verification.”
Patrick Sheridan of Synopsys, Inc. was a strong proponent of virtual prototypes for software development, software-hardware co-development, and architectural design. He stressed the importance of performance estimation in ESL, especially utilizing the new IEEE 1801-2015 UPF 3.0 standard which includes power. His position was: “UPF 3.0, system-level power modeling and analysis using power-aware virtual prototypes are enabling architects and system designers to define systems that yield the greatest benefit in terms of energy efficiency, months earlier, before hardware is available.” He also agreed that the virtual platform/prototype part of ESL needs to be better integrated with the rest of the chip development process.
Adnan Hamid of Breker Verification Systems, Inc. focused on the upcoming portable stimulus standard from Accellera, which spans multiple levels of abstraction from ESL models all the way to silicon. His position was that automatic generation of portable test cases is already enabling faster development of higher quality SoC designs, and that having a standard for common stimulus for virtual platforms, RTL models, etc. will help make ESL mainstream. He believes that this advancement is comparable in significance to the development of design synthesis.
Raik Brinkmann of OneSpin Solutions GmbH talked about the power of ESL in verification, how verifying designs at a high level of abstraction helps find both implementation bugs and higher-level design errors, potentially saving weeks downstream in the process. He also agreed that ESL must address the system verification problem, including both hardware and software.
Provocative audience questions included:
- “Does an ESL solution, especially SystemC, require a huge investment and therefore can only be adopted by big companies? It seems to require so much infrastructure! How can small companies deploy ESL, do we need to boil the ocean?” Simon’s answer was that virtual platforms are accessible, affordable and available for the whole market, both large and small companies. Dave agreed that there is no need to “boil the ocean;” incremental adoption of ESL technologies is possible and valuable.
- “Is “ESL” defined as a solution without bringing in the most important people, the software developers?” Simon agreed that EDA in general needs to incorporate software development; especially software that is close to the hardware, which virtual platforms do support. He proposed a call to action for more focus on hardware dependent software.
- “What happens to my verification job as we move to high level verification? I fear for my livelihood!” Panelists noted that verification jobs will not only persist, but will become more interesting and powerful when working at higher levels of abstraction, catching more critical bugs.
- “I want to wait till my RTL is done and then abstract a high level model for software development which does not start until after the hardware is already done. How can I do this?” Panelists noted that reliable technology for this is not available, but also challenged the idea of waiting until hardware is completed before starting software development because clearly this extends the overall development flow.
In summary, there is a huge need for (let’s call it ESL) technology to span embedded software and all levels of hardware design, supporting architectural performance and power analysis, early software development, synthesis from high-level to implementation-level hardware descriptions. As Brian noted, Gary Smith’s long held dream….
Despite a lack of consensus on a clear definition of ESL, it seems that it is comprised of the key technologies of:
- Virtual platforms / virtual prototypes for architectural modeling, performance analysis, early software development and testing, and hardware verification.
- High-level synthesis from a model at a higher level of abstraction than RTL.
In particular, today virtual platforms are readily available and powerful tools for operating at an “ESL” level, integrating hardware and software. New UPF extensions for power analysis will extend their utility. Portable stimulus should help integrate them with downstream verification requirements.
However, these technologies have not been fully adopted by developers, fully developed by vendors, and unified in a flow; so there is lots of opportunity, and much to be done in the world of ESL!
For more on this topic, see Brian Bailey’s article titled, “What ESL Is Really About.”