ITC2016 Call for Posters

Call for Posters

ITC2016, which will be held Nov 15 - 17  at the Fort Worth Convention Center in Fort Worth Texas, is now accepting one-page abstracts for the poster session. These abstracts are used for the selection process, and will not be published.  The poster session will be held on the Exhibits Floor at the Fort Worth Convention Center on Wednesday November 16 from 12 noon to 2 p.m. 


Important dates are:

  • Submission Window Open: Now
  • Submission Deadline: Monday  June 27
  • Author Notification: Friday, August 1


Posters are a useful way of presenting late-breaking results, getting feedback on an innovative method, or participating  without having to write a full paper. Each poster should describe test-related innovations. Poster contributors must be present at their poster display to engage in technical discussions with the attendees.

The Poster Session is available to conference attendees and exhibitors, and is a good opportunity for exposure. Poster sessions in the past have been well attended and highly interactive. Successful poster submissions can be the basis for a future ITC conference paper. Acceptance as a poster does not preclude submission of a more complete treatment as an ITC paper in 2017 (and beyond). 

Feel free to base your abstract/proposal on any of the suggested topics in the right-hand column. We welcome ideas that are not on this list, and will give them equal consideration.

Please visit the ITC Website to submit abstracts/proposals or to view submission instructions. If you have any questions please contact . Li C. Wang


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Conference Focus Topics

  • Test- and Design-for-Manufacturability
  • Yield Analysis and Optimization
  • Embedded Instruments (BIST & DFT)
  • Reliability Screening
  • Low-Cost Test
  • Diagnosis and Silicon Debug
  • High-Speed I/O and RF Test
  • Probecard Design
  • Self-Repair and Fault Tolerance
  • System Test and False Positives
  • Experiments and Case Studies
  • Component-in-System Test

Hot Topics

  • 3-D/TSV (Through-Silicon Vias)
  • Adaptive Test
  • Board Test
  • Defect-based Testing
  • Innovative Industrial Test Practices
  • Fault Modeling, Simulation and Test
  • Power Issues in Test
  • Standalone Memory Test and Repair
  • ATE Hardware and Software
  • Online Test
  • Protocol-aware Test
  • Post-Si Validation
  • Test Resource Partitioning
  • Test Flow Optimization

Regular Topics

  • Automatic Test Generation
  • Boundary-Scan 
  • On-Chip Test Compression
  • Economics of Test
  • Fault Modeling and Simulation 
  • Online Test 
  • IDDQ and Current Test
  • Interface Issues
  • Microprocessor Test
  • Mixed-Signal and Analog Test
  • Multisite Test
  • System-in-Package and KGD Test
  • Test Standards
  • Test Quality and Reliability


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