Rambus to Showcase SerDes and Memory PHY Solutions at DesignCon

Experts to present two technical sessions addressing verification and power efficiency and additional technical trainings explore system design challenges for memory and serial links

SUNNYVALE, Calif. — (BUSINESS WIRE) — January 24, 2017Rambus Inc. (NASDAQ: RMBS):


Rambus Inc. (NASDAQ: RMBS)

Where: DesignCon
Booth #833
Santa Clara Convention Center
5001 Great America Pkwy
Santa Clara, CA 95054
When: January 31 – February 2, 2017 (Conference)
February 1 – 2, 2017 (Expo)

Join Rambus at DesignCon for product demonstrations showcasing its comprehensive suite of Ethernet, PCIe and DDRn IP solutions to solve today’s most challenging data center and networking applications. Rambus technical experts, executives and partners will also be holding a series of talks and technical training sessions listed below.

Rambus Technical Session Details:
Title: Power Delivery Network Design and Optimization for High-Speed Systems with Si Interposer
Date: Wednesday, February 1, 2017
Time: 9:00 am – 9:45 am
Location: Ballroom A
Speaker: Wendem Beyene, Technical Director, Rambus

Title: Methodology for Reusing the Verification Tests and Efforts Beyond Pre-silicon Verification
Date: Thursday, February 2, 2017
Time: 3:00 pm – 3:45 pm
Location: Ballroom C
Speakers: Dinesh Malviya, Sr. Manager Engineering, Rambus; Sujith Hiremath, Senior Member of Technical Staff - Verification, Rambus

Rambus Training Sessions:
Title: An 8b ADC for a 56Gbps PAM4 Receiver
Date: Wednesday, February 1, 2017
Time: 9:20 am – 10:00 am
Location: Great America 3
Speakers: Kenneth C. Dyer, Senior Principal Engineer Architect, Rambus; Shankar Tangirala, Principal Design Engineer, Rambus

Title: ADC-Based Link Architecture for Multilevel Signaling at 56G

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