Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff

Signal analysis capability also included to handle increasingly complex high-speed interconnect designs, including PCIe 4.0

SAN JOSE, Calif., Jan. 25, 2017 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced availability of the Sigrity 2017 technology portfolio, which introduces several key features specifically designed to speed up PCB power and signal integrity signoff. Among the features included in the newest version of the Cadence® Sigrity portfolio are the Allegro® PowerTree topology viewer and editor, which enable designers to quickly assess power delivery decisions early in the design cycle. The latest release of Sigrity also includes a PCI Express® (PCIe®) 4.0 compliance kit for checking signal integrity compliance with the latest PCIe specification when it is certified later this year.

The ability to accelerate PCB power and signal integrity signoff is not only critical for designing standalone circuit boards, but is also an important element for designing complete end products. Sigrity 2017 is one of Cadence's System Design Enablement technologies helping companies to create innovative, high-quality electronic products from chips, to boards, to entire systems. More detail on the Sigrity 2017 portfolio may be found at cadence.com/go/Sigrity2017.

Determining the path for power delivery early in the design cycle is critical to PCB design teams. The PowerTree user interface uniquely allows for a power topology to be viewed for quick and accurate determination of the best path for power delivery. The technology also allows for easy editing as designs change. The information stored in the PowerTree environment is then used later in the design cycle to provide automated setup of post-route power integrity analysis for faster closure.

Also included in the Sigrity 2017 release is library management for power integrity models through the analysis model manager. Models can be saved and automatically retrieved from the analysis model manager library when design components are reused. This method also speeds development by automating processes that in the past have been repeatedly carried out manually.

The Sigrity 2017 release also helps designers incorporate the latest PCIe technology for high-speed interconnect as they work to ensure signal integrity. It includes a compliance kit for PCIe 4.0 interfaces in the Sigrity SystemSI Serial Link Analysis tool to automatically qualify signal quality standards instead of manually checking and measuring against standards documents.

"The Sigrity 2017 portfolio includes technology designed to increase efficiency and speed up the design process," said Steve Durrill, Senior Product Engineering Group Director, Cadence. "Each of the features we've updated have been improved with the goal of helping our customers get high-performing products out the door faster. The work we've done to develop the PCIe 4.0 compliance kit even before the standard has been ratified is a visible and important example of this focus on customer requirements and time to market."

"Teradyne has worked closely with Cadence to enable our PCB designers to take a more active role in power integrity design," said Paul Carlin, Design Technology Group Manager. "The new updates to the Sigrity portfolio will help improve efficiencies to accelerate our product development time. This is an important advantage for Teradyne."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

This news release contains certain forward-looking statements that are based on our current expectations and involve numerous risks and uncertainties that may cause these forward-looking statements to be inaccurate. Risks that may cause these forward-looking statements to be inaccurate include, among others, the risks detailed from time-to-time in our U.S. Securities and Exchange Commission filings and reports, including, but not limited to, our most recent quarterly report on Form 10-Q and our annual report on Form 10-K. We do not intend to update the information contained in this news release.

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI Express and PCIe are registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/cadence-sigrity-2017-delivers-fast-path-to-pcb-power-integrity-signoff-300396413.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




Review Article Be the first to review this article
Aldec


Featured Video
Editorial
More Editorial  
Latest Blog Posts
Modesto (Mo) CasasGlobal Business in EDA
by Modesto (Mo) Casas
Focus a Global Reseller Channel on Your Product
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Functional Safety and Security in Embedded Systems
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Phil Kaufman Award Goes on Hiatus for 2020
Colin WallsEmbedded Software
by Colin Walls
Why develop embedded software bottom up?
Jobs
Product Line Manager for EDA Careers at Multiple, North Carolina
ASIC Design Engineer, for Apple Inc at Cupertino, California
ASIC Engineer for Amazon at seattle, Washington
Senior Java Developer/Architect for EDA Careers at Varies, North Carolina
Senior Analog IC Design Engineer for Marvell Semiconductor at Santa Clara, California
ASIC Design Integration Engineer for Apple Inc at Cupertino, California
Upcoming Events
Accellera Day India 2020 at Online Event India - Dec 2 - 3, 2020
RISC-V Summit 2020. at United States - Dec 7 - 10, 2020
SEMICON Japan 2020 Goes Virtual at Japan - Dec 11 - 18, 2020
IPC APEX EXPO 2021 at San Diego Convention Center san diego - Mar 6 - 11, 2021
Verific: SystemVerilog & VHDL Parsers
TrueCircuits:



© 2020 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise