Si2 Contributes Advanced IC Power Modeling Technology to IEEE

Technology will improve System-on-Chip (SoC) design for power efficiency

AUSTIN, Texas — (BUSINESS WIRE) — April 11, 2017 — Silicon Integration Initiative, Inc. (Si2), a leading integrated circuit research and development joint venture, has contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at creating a standardized means for modeling systems-on-chip (SoC) designed for lower power consumption.

Jerry Frenkil, Si2 director of OpenStandards, said that the Si2 Low Power Working Group developed the new technology to fill several holes in the flow for estimating and controlling SoC power consumption. “This new modeling technology provides accurate and efficient, early estimation of both static and dynamic power, including critical temperature dependencies, using a consistent model throughout the design flow. There’s currently no standard way to represent power data for use at the system level, especially across a range of process, voltage and temperature points in a single model.”

IEEE P2416 is an essential component of IEEE’s coordinated effort to improve system-level design. This effort also includes the IEEE 1801 standard, which expresses design intent. Its latest update, IEEE 1801-2015, includes support for power-state modeling. “P2416 provides power data representations to complement 1801 power-state modeling. Together, 1801 and 2416 will form a complete power model for hardware IP at any level of abstraction,” Frenkil added.

Organizations that contributed to the model development are: ANSYS, Cadence, Intel, IBM, Entasys, and North Carolina State University.

Nagu Dhanwada, senior technical staff member at IBM, chairs both the IEEE P2416 and Si2 Power Modeling Working Groups. According to Dhanwada, “This is a major contribution to the P2416 effort. As the first technology contribution to the P2416 Working Group, it’s expected to form a solid foundation for the resulting standard.”

“This new modeling technology is the first significant advance in power modeling in quite a long time,” said Paul Traynar, technical fellow at ANSYS and a contributor to the Si2 effort. “It will enable SoC designers to get consistent power estimates across design abstractions and especially early in the system design process.”

Julien Sebot, CPU architect at Intel and a member of the IEEE P2416 Working Group, added, “The Si2 contribution addresses the top priorities identified by the P2416 Working Group. The ability to create accurate, early estimates and to reuse and refine those estimates during the design process is essential in creating energy efficient systems-on-chip. Si2’s contribution is a major step toward addressing that need.”

The IEEE P2416 Working Group has already started reviewing the Si2 contribution. In parallel, Si2 will further develop, for its members, the technology with expanded model semantics, proof-of-concept demonstrations, and reference design implementations.

This model and its use will be described as part of a DAC 2017 tutorial, “How Power Modeling Standards Power Your Designs,” Monday, June 19, 3:30-5:00 p.m., Room 18AB, Austin Convention Center.

For more information about this project, contact Jerry Frenkil at Jfrenkil@si2.org. For information about the Si2 Low Power Working Group and other OpenStandards programs, visit http://www.si2.org/openstandards/.

Founded in 1988, Si2 is a leading research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. All Si2 activities are carried out under the auspices of the National Cooperative Research and Production Act of 1993, the fundamental law that defines R&D joint ventures and offers them a large measure of protection against federal antitrust laws. Si2’s international membership includes semiconductor foundries, fabless manufacturers, and EDA companies.



Contact:

Silicon Integration Initiative, Inc.
Terry Berke, 512-917-1358
Email Contact




Review Article Be the first to review this article

 Advanced Asembly

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
You’re Invited! SEMI’s Innovation for a Transforming World
intelThe Dominion of Design
by intel
The Long Game: Product and Security Assurance
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Setting a High Standard for Standards-Based IP
Jobs
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
Technical Product Manager- SISW-EDA 238452 for Siemens AG at Fremont, California
SerDes Applications Design Engineer for Xilinx at San Jose, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
Circuit Design & Layout Simulation Engineer - Co-Op (Spring 2021) for Global Foundaries at Santa Clara, California
Upcoming Events
Join Chipx2021 - at Tel Aviv Expo convention center Tel Aviv Israel - Jun 21 - 22, 2021
Innovation for a Transforming World -virtual Event at United States - Jul 13 - 14, 2021
DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021
SEMICON Southeast Asia 2021 Hybrid Event at Setia SPICE Convention Centre Penang Malaysia - Aug 23 - 27, 2021



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise