Faraday Introduces UrLib+™ Add-on Library on UMC 40LP Process

HSINCHU, Taiwan, May 16, 2017 - Faraday Technology Corporation (TWSE: 3035), a leading ASIC design service and IP provider, today introduced its new  UrLib+™ add-on library for the third-party library on UMC 40LP process technology.  UrLib+ is a library package, featuring extra sets of cells for optimized PPA (Power/Performance/Area), yield controllability, clock tree noise reduction, robust ESD protection, and lower ECO cost over the traditional physical libraries.

By utilizing Faraday’s 24-year experiences in library development and ASIC implementation, UrLib+ can be seamlessly integrated with the existing third-party library on UMC 40LP process to improve the routing results and yield for mass production. With UrLib+ supported, the CPU core can save around 43% of clock tree power and up to 15% of total power. For the routability efficiency, UrLib+ can shrink the die size from 4% to 11% depending on the design architecture and cell mapping flow. UrLib+ solution is not only dedicated for 40LP, Faraday also supports UrLib+ porting service for other third-party libraries or technology platforms.

“Library design is the foundation of IC design. Driven by ASIC product diversification, Faraday always has unique ideas and practices in library design,” said Steve Wang, President of Faraday. “In the UMC's advanced processes, the continuous realization of the library improvements is our persistent goal. We believe UrLib+ is a win-win-win solution for IC design house, fab, and third-party library vendor.”

About Faraday Technology Corporation

Faraday Technology Corporation (TWSE: 3035) is a leading ASIC design service and IP provider. The broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDR2/3/4, low-power DDR1/2/3, MIPI, V-by-One, USB 2.0/3.1 Gen 1, 10/100/1000 Ethernet, Serial ATA, PCI Express, and programmable SerDes, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, visit  www.faraday-tech.com.

 


Contact:

Faraday Tech
Evan Ke
886.3.578.7888 ext. 8689
Email Contact




Review Article Be the first to review this article
Aldec


Featured Video
Editorial
Roberto FrazzoliEDACafe Editorial
by Roberto Frazzoli
Intel’s new CEO: comments from media and analysts
More Editorial  
Jobs
Product Line Manager for EDA Careers at Multiple, North Carolina
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
SerDes Applications Design Engineer for Xilinx at San Jose, California
Senior Application Engineer Formal Verification for EDA Careers at California or Austin, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
Upcoming Events
Si2 AI/ML Winter Workshop at United States - Jan 29, 2021
virtual DATE 2021 at France - Feb 1 - 5, 2021
SEMI Technology Unites Global Summit at United States - Feb 15 - 19, 2021
DVCon U.S. 2021 at Virtual - Mar 1 - 4, 2021



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise