Sidense SHF Memory Macros Target IoT and Other Very Low Power Applications in TSMC's 40ULP Process

OTTAWA, ON--(Marketwired - May 23, 2017) - Sidense Corp., a leading developer of non-volatile memory (NVM) IP cores, today announced that the Company's 1T-NVM macros for TSMC's 40ULP process have met all TSMC9000 IP Quality Management Program requirements. Applications for Sidense SHF memory IP include code storage, ROM replacement, secure encryption key storage, configuration, fuse replacement, trimming and calibration.

"We developed SHF 1T-NVM macros for TSMC's 40ULP process node to enable our customers designing ICs for IoT and other applications that demand very low power consumption and low operating voltage," said Andrew Faulkner, Senior Director of Product Marketing at Sidense. "Our macros also feature high reliability, field programmability and strong data-in-place security, important attributes for embedded memory designed into devices for the Smart Connected universe."

Optimized for high-performance and a wide range of bit densities, Sidense SHF macros are available for standard CMOS processes. There are no requirements for any additional masks or processing steps.

Besides being qualified at 40ULP at a 1.1V core voltage, Sidense has also met TSMC9000 IP Quality standard requirements for TSMC's 40LP process node and is about to tape out macros for 40ULP with a 0.9V core voltage.

About SHF
SHF memory IP is a complete, non-volatile memory (NVM) subsystem providing interfaces and features to support a range of embedded integrated circuit applications. SHF macros feature high security, very low power, fast programming speed, field-programmability, low-read voltage and several read modes to optimize read performance and macro area. The SHF module integrates the OTP memory and Integrated Power Supply (IPS) hard macro blocks along with program control, programming and test interface, error correction and Built-In Self-Test (BIST) supplied in RTL.

SHF is a well-proven design having already been deployed in high volume at 40nm. As the chosen solution for advanced nodes, SHF 1T bit-cell architecture development is at an advanced stage in more leading-edge nodes down to 16nm FinFET. SHF memory macros are suitable for a wide range of Smart Connected applications from mobile communications to the expanding IoT ecosystem

About Sidense Corp.
Sidense Corp. provides very dense, highly reliable, and secure Logic Non-Volatile Memory (LNVM) IP for one-time programmable (OTP) and emulated Multi-time Programmable (eMTP) use in standard-logic CMOS processes. The Company, with over 120 patents granted or pending, licenses OTP memory IP based on its innovative one-transistor 1T-Fuseā„¢ bit cell, which does not require extra masks or process steps to manufacture. Sidense 1T-NVM macros provide a better field-programmable, reliable and cost-effective solution than flash, mask ROM, eFuse and other embedded and off-chip NVM technologies for many code storage, encryption key, analog trimming, and device configuration uses.

Over 150 companies, including many of the top fabless semiconductor manufacturers and IDMs, have adopted Sidense 1T-NVM as their embedded non-volatile memory solution for more than 500 designs. Customers are realizing outstanding savings in solution cost and power consumption along with better security and reliability for applications ranging from mobile and consumer devices to high-temperature, high-reliability automotive and industrial electronics. The IP is offered at and supported by all top-tier semiconductor foundries and selected IDMs. Sidense is headquartered in Ottawa, Canada with sales offices worldwide. For more information, please visit www.sidense.com.




Media Contacts:
Susan Cain
Cain Communications for Sidense
Tel: 408-393-4794
Email: 
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Jim Lipman
Sidense
Tel: 925-606-1370
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