FREIBURG, Germany — (BUSINESS WIRE) — June 15, 2017 — Concept Engineering, leaders in visualization and debugging technology for electronic circuits and systems, will unveil version 6.7 to the company′s popular Vision platform at the Design Automation Conference (DAC) in Austin, Texas, in June 2017.
The new features in version 6.7 of Concept Engineering’s Vision Debugging platform, improves the exploration and debug of Verilog AMS designs, makes RTL design and debug faster and more efficient and improves SPICE-level debugging, among other new functions. Concept Engineering representatives will demonstrate the new features at the upcoming Design Automation Conference (DAC) to designers of analog, digital, mixed-signal circuits and systems-on-chip (SoCs).
Concept Engineering’s Vision Debugging platform consists of three individual tools for specific design styles and abstraction levels:
- SpiceVision® PRO for device-level debugging (SPICE-level debugging)
- GateVision® PRO for full chip netlist debugging (Gate-level debugging)
- RTLvision® PRO for easy RTL code exploration, SoC/IP integration and debugging (RTL code debugging)
The three individual tools are complemented by Concept Engineering’s flagship tool StarVision® PRO, which combines the individual debugging features of all Vision tools into one customizable mixed-signal and mixed-language platform with powerful debugging and flow automation capabilities for the design of complex SoCs, ASICs, IoT devices or mixed-signal silicon chips.
"With version 6.7, we continue to improve our Vision product family and help our customers to find bugs earlier and faster," said Gerhard Angst, president and CEO of Concept Engineering. "We are proud to deliver significant improvements for mixed-signal designers and provide RTL design engineers with smarter RTL exploration and improved RTL debugging capabilities."
Notable Enhancements for Mixed-Signal Design/Debugging:
- Support to read mixed-signal Verilog AMS designs has been added. This offers exciting new options to explore and debug complex analog, mixed-signal, IoT and RF integrated circuits.
- The tools perform a more relaxed language checking while reading complex SoCs. This allows improved handling of incomplete designs where IP building blocks are not yet properly defined, but engineers must still be able to start to analyze the system while it's under construction.
Notable Enhancements for RTL Design/Debugging:
- The RTL source view window has been improved significantly. We introduced “Action Bar" for easy object specific navigation within complex RTL source code files.
- Several changes have been made to improve memory consumption and speed while reading RTL code (System Verilog, Verilog and VHDL).
- The RTL parsers do a more relaxed language checking.
- We now offer easy display of RTL source code fragments in the schematic window using instant tooltips.
- The integrated waveform viewer has been extended and optimized.
Notable Enhancements for SPICE-level Design/Debugging:
- We improved netlist parsing for Mentor Graphics’ Eldo and Cadence’s Spectre SPICE dialects.
- Many enhancements and fixes for post-layout debugging (SPEF and DSPF parser enhancements) have been made.
- The SPICE netlist export interface has been extended and improved.
Notable Enhancements for design flow automation:
- We extended and enhanced our database APIs and GUI APIs to support more sophisticated code to be developed and executed by the tool platform. Batch processing and customized GUI commands allow company specific – or project specific - debugging tasks and flow automation.
StarVision® PRO, RTLvision® PRO, GateVision® PRO, and SpiceVision® PRO are customizable and scriptable debugging and visualization software tools that help electronic design engineers to easily understand, debug, optimize and document their designs.
StarVision PRO provides analog, digital and mixed-signal debugging capabilities, customizable design rule checks and automated netlist pruning.
RTLvision PRO is used for RTL debugging and intellectual property (IP) development.
PRO for advanced netlist debugging of complex SoC netlists.