Excellicon Deepens the Verification of Timing Intent Exceptions

June 15, 2017 - Laguna Hills, CA -- Excellicon Inc. an innovative and number one provider of end-to-end timing constraints analysis and verification products announced new capabilities to its “Exceptions Toolbox” product for automated validation of timing exceptions which includes structural as well as timing intent class of false and multi-cycle paths. The users of Excellicon products can now very simply and automatically validate their existing timing exceptions comprehensively.

In a typical SOC design as part of design implementation there is often a need to define timing exceptions to address timing issues of the design at early and/or later design stages. Generally about 80% of such timing exceptions are of the timing intent nature, with remaining 20% being structural. Timing exceptions provide directives to static timing tools to adhere to certain timing constraints for timing analysis.  In the past, validation of structural exceptions has been achieved by path tracing and formal analysis of violating paths. However, the Timing intent exception validation where designer provides his “Intent” in terms of timing and how the circuit should behave has been very challenging.

Exceptions Toolbox (ET) in addition to full formal structural exception capabilities, provides a proprietary and patent pending algorithms for validation of Timing Intent based False Paths (FP) and Multi Cycle Paths (MCP) at RTL and Gates. Generally the Timing Intent Exceptions cannot be validating formally. Exceptions tool-box can identify the type of exceptions and through proprietary methods generate the appropriate simulation setup information which can then be simulated for validation of such exceptions.

For the first time designer using ET are empowered to generates special outputs that is used to validate Timing Intent class of exceptions. In addition for structural class of exceptions, ET generates SVA's that are independent of the formal algorithm that is used to verify the exceptions. This provides a mechanism to the user to verify all exceptions in the SDC with 100% confidence.

“For the most part the Timing Intent Exceptions today are verified manually and through inspection. What ET brings to the table a methodical and automated approach to solving a big gap in validation of timing constraints. Since a vast majority of exceptions for a typical design are of Timing Intent type, by systematically validating such exceptions the risk is significantly lowered for the final set of timing constraint developed for signoff.” Said Rick Eram, VP of marketing at Excellicon.

About Excellicon

Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of timing constraints authoring, compilation, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products CONstraints MANager, CONstraints CERTifier, , and ConCert-ET (Exceptions Toolbox) address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right! 

For further information contact:
Rick Eram
www.excellicon.com



Read the complete story ...


Review Article Be the first to review this article
DAC 2020

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Meet the New Cylynt, Fighting Software Piracy Around the Globe
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Jobs
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Software Engineer for EDA Careers at RTP, North Carolina
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Upcoming Events
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020
Drive World Conference & Expo at Santa Clara Convention Center Santa Clara CA - Aug 11 - 13, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise