Spectral announces "Enablement Package" for Silicon proven Reference SRAM designs on advanced process nodes

SOMERVILLE, NJ--(Marketwired - June 16, 2017) - Spectral Design & Test Inc. (SDT) today announced a complete reference flow on advanced process nodes that enables customers to quickly create industrial strength SRAM Memory Compilers. A combination of Spectral's proprietary Memory Development Platform (MDP) with a state of the art high-density low power architecture, customers can quickly create behavioral models, testbenches, schematics, layouts, timing, power & test views. Significant amount of time is spent in developing and maintaining software & hardware infrastructure necessary to create Memory Compilers. A reference design proven in silicon encapsulated in MDP gives designers a jump-start to create Memory Compilers without writing complex array tiling, analysis and characterization software. Spectral's reference designs can be seamlessly targeted on bulk-CMOS, FinFet & FDSOI processes. Spectral's MDP software is enabling customers to develop differentiated memory design and Memory Compiler creation at advanced technology nodes. Spectral software tools like MemoryCanvas™, MemoryTime™, MemComp™ have hooks to standard EDA tools ensuring that the customer's existing infrastructure is fully leveraged.

"Extreme requirements for high capacity low power SRAMs coupled with complicated design rules in the advanced nodes has significantly extended the cycle time, it is imminent that productivity gains are required for time-to-market and contain labor costs," said Deepak Mehta President & CEO of SDT. "We offer SOC library developers the best in class tools to create Memory Compilers that can be used to create design blocks internally and can be distributed license free to their end customers." Additionally, Spectral software comes with features that facilitate library developers to encrypt, license IP and distribute the Memory Compilers encapsulated in a very easy to use GUI. Spectral will demonstrate the development and delivery of Memory Compilers at the Design Automation Conference (DAC) 2017 by showcasing their products on the 16 & 40nm process nodes.


Spectral tools are developed & fully verified on an OpenAccess database (Si2 organization). SDT is a member of Cadence, Mentor Graphics & Synopsys partnership and eco systems.

William Palumbo 

Review Article Be the first to review this article

Featured Video
Latest Blog Posts
Colin WallsEmbedded Software
by Colin Walls
Selecting a CPU
Product Applications Engineer for DiCon Fiberoptics, Inc. at Richmond, California
Mid to Senior Level Electrical Engineer for Gordon Prill, Inc at Santee, California
Principal Engineer, Firmware Engineering for Western Digital at Milpitas, California
Sr. Electrical Hardware Project Engineer for Stellartech Research Corp at Milpitas, California
Nano-Optics Process Engineer for DiCon Fiberoptics, Inc. at Richmond, California
Team-Lead - Image Production (m/f/d) for Vexcel-Imaging GmbH at Graz, Austria
Upcoming Events
MEMS & Imaging Sensors Summit at World Trade Center Grenoble France - Sep 25 - 27, 2019
2019 Electronic Design Process Symposium at Milpitas CA - Oct 3 - 4, 2019
Embedded Systems Week (ESWEEK) at New York City NY - Oct 13 - 18, 2019

Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise