MEDIA ALERT: Credo Demonstrates Single-Lane 112G and 56G PAM4 SerDes IP Solutions at TSMC 2017 OIP Ecosystem Forum

MILPITAS, CA--(Marketwired - September 13, 2017) - Credo Semiconductor, a global innovation leader in Serializer-Deserializer (SerDes) technology, today announced it will demonstrate its full offering of advanced SerDes IP at this week's TSMC Technology Symposium, showcasing single-lane 112G PAM4 SerDes solutions.

The wide range of Credo SerDes IP solutions enables ASIC, ASSP, and SoC designers to meet the power and performance requirements of a variety of TSMC advanced processing nodes and supports emerging IEEE standards including 802.3cd/802.3bs/802.3bm which call out 100GBase-DR1, 400GBase-DR4, and 400GBase-FR4.

WHERE:
TSMC Open Innovation Platform Ecosystem Forum
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054
Booth #907

WHEN:
September 13, 2017
8:00 a.m. - 6:30 p.m.

WHAT:
The TSMC OIP Ecosystem Forum brings together TSMC's design ecosystem companies and our customers to share practical, tested solutions to today's design challenges. Success stories that illustrate TSMC's design ecosystem best practices highlight the event.

About Credo Semiconductor
Credo is a leading provider of high performance, mixed-signal semiconductor solutions for the data center, enterprise networking and high-performance computing markets. Credo's advanced Serializer-Deserializer (SerDes) technology delivers the bandwidth scalability and end-to-end signal integrity for next generation platforms requiring single-lane 25G, 50G, and 100G connectivity. The company makes its SerDes available in the form of Intellectual Property (IP) licensing on the most advanced process nodes and with complementary product families focused on extending reach and multiplexing to higher data rates. Credo is headquartered in Milpitas, California and has offices in Shanghai and Hong Kong. For more information: www.credosemi.com




Press Contact:

Jen Peckham

Email Contact





Review Article Be the first to review this article
Aldec


Latest Blog Posts
Michelle Mata-ReyesAldec Design and Verification
by Michelle Mata-Reyes
ARM-based SoC Co-Emulation using Zynq Boards
Jobs
Senior Software Architect Internet for EDA Careers at San Jose, California
Salesforce Technical Lead   East Coast  for EDA Careers at Cherry Hill, New Jersey
Sr. Application Engineer for Mentor Graphics at Fremont, California
Hardware Engineer, Board Design for Arista Networks at Santa Clara, California
Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
Upcoming Events
FLEX 2020 and MSTC 2020 at DoubleTree by Hilton 2050 Gateway Place San Jose CA - Feb 24 - 27, 2020
DVCon U.S. 2020 at DoubleTree Hotel San Jose CA - Mar 2 - 5, 2020
OFC 2020 - The Optical Networking and Communication Conference & Exhibition at San Diego Convention Center San Diego CA - Mar 8 - 12, 2020
DATE '2020 at ALPEXPO Grenoble France - Mar 9 - 13, 2020



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise