Cadence Introduces the Conformal Smart Logic Equivalence Checker

Massively parallel architecture and adaptive proof technology improve equivalence checking runtime by an average of 4X

SAN JOSE, Calif., Sept. 13, 2017 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Cadence® Conformal® Smart Logic Equivalence Checker (LEC), the next-generation equivalence checking solution that delivers a significant improvement in equivalence checking runtime with minimal user effort. The Conformal Smart LEC delivers an average of 4X runtime improvement compared to the previous generation of logic equivalency checking tools with the same compute resources.

Cadence Logo. (PRNewsFoto/Cadence Design Systems, Inc.) (PRNewsFoto/CADENCE DESIGN SYSTEMS_ INC_) (PRNewsFoto/CADENCE DESIGN SYSTEMS, INC.)

For more information on the Conformal Smart LEC, visit www.cadence.com/go/conformalsl.  

With rapidly growing chip functionality, design sizes are increasing. In addition, with the latest advances in logic synthesis at advanced nodes, designers employ aggressive synthesis techniques to achieve power, performance and area (PPA) goals. These advances in both design size and complexity stress equivalence checking proof methods and can result in long runtimes and sometimes inconclusive results. Equivalence checking is a critical step in digital tapeout flows, and the Conformal Smart LEC solution addresses these issues. The key technology components of the Conformal Smart LEC are:

  • Massively parallel architecture automatically partitions designs and distributes formal proof strategies across multiple machines and CPUs, and can scale seamlessly to 100s of CPUs for improved runtime. This process is fully transparent to the user and does not require manual configurations.
  • Adaptive proof technology finds the fastest solution to a conclusive proof with minimal user effort. It analyzes each partition and determines the optimal formal algorithm to use to minimize runtime and avoid proof timeouts—especially on designs with complex behavioral datapath components. 

"We've already seen several customers achieve significant runtime improvements and aggressive PPA goals with the Cadence Conformal Smart LEC," said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. "Additionally, our massively parallel architecture and adaptive proof technologies for equivalence checking reduce the need for manual tasks so customers can deliver complex designs to market faster."

"For complicated designs including deep logic cones, it often used to take multiple expert user iterations per block to prove RTL-to-gate logic equivalence," said Hideyuki Okabe, senior manager, Digital Design Technology Department, Shared R&D Division 2, Broad-Based Solution Business Unit at Renesas Electronics Corporation. "The Cadence Conformal Smart LEC automatically identifies the right proof strategy and has reduced these iterations to just one. Also, the Conformal Smart LEC's massively parallel architecture has enabled us to reduce our average runtime by 4X. With our designs moving to smaller process nodes and continuing to grow in size and complexity, this technology is crucial to meet our current and future time-to-market goals."

The new Conformal Smart LEC further extends the innovation within the Cadence digital design and signoff suite and supports the company's broader System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company's System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at  cadence.com.

© 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com

 

View original content with multimedia: http://www.prnewswire.com/news-releases/cadence-introduces-the-conformal-smart-logic-equivalence-checker-300518609.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




Review Article Be the first to review this article
DAC 2020

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Modesto (Mo) CasasGlobal Business in EDA
by Modesto (Mo) Casas
The Contingent Purchase Order Reassures Buyer and Seller
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Meet the New Cylynt, Fighting Software Piracy Around the Globe
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Jobs
Senior Physical Design/Layout Engineer for EDA Careers at EAST COAST, California
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Digital Design ASIC Manager for EDA Careers at RTP, North Carolina
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Upcoming Events
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020
Drive World Conference & Expo at Santa Clara Convention Center Santa Clara CA - Aug 11 - 13, 2020
TrueCircuits:



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise