Cadence Collaborates With TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation

Highlights:

  • Cadence digital, signoff and custom/analog tools achieve latest DRM and SPICE certifications for TSMC 5nm and 7nm+ process technologies
  • Digital, signoff and custom/analog tool capabilities improve 5nm and 7nm+ designer productivity
  • Cadence library characterization tool flow supports 5nm and 7nm+ process

SAN JOSE, Calif. — (BUSINESS WIRE) — May 1, 2018 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence® digital, signoff and custom/analog tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for the TSMC 5nm and 7nm+ processes. The corresponding process design kits (PDKs) are now available for download.

To learn more about the Cadence full-flow digital and signoff advanced-node solutions, visit www.cadence.com/go/tsmc5and7nm+dands. For information about the Cadence custom/analog advanced-node solutions, visit www.cadence.com/go/tsmc5and7nm+canda.

5nm and 7nm+ Digital and Signoff Tool Certification

Cadence provides a fully integrated digital flow from implementation to final signoff that has been certified by TSMC for the latest versions of the 5nm and 7nm+ processes. For the 7nm+ process, the Cadence full-flow includes the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer. For the 5nm process, the Cadence certified tools include the Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, the layout vs. schematic (LVS) function in PVS and LDE Electrical Analyzer.

Cadence digital and signoff features available for the 7nm process are also available for the 5nm and 7nm+ process. Some of these features include cut-metal handling throughout the design flow, via-pillar support, clock mesh and bus-routing. These capabilities can enable customers to successfully design mobile and HPC systems with improved power, performance and area (PPA) while reducing iterations and achieving their cost and performance objectives.

In addition, Cadence has delivered new enhancements focused on EUV support at key layers and associated new design rules that specifically support the 5nm and 7nm+ processes. Some of the other newest enhancements for the 7nm+ process include cell pin support, Self-Heating Effect (SHE) and heatsink support.

Specifically for the 5nm process, Cadence digital and signoff tools offer high-resistance resistor support, router compliance for new rules and new extraction support including additional resistor layer modeling and other middle end-of-line (MEOL) features.

5nm and 7nm+ Custom/Analog Tool Certification

The certified custom/analog tools include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF, and Spectre Circuit Simulation, as well as the Virtuoso® product suite, which consists of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment.

By using the latest capabilities and design methodologies included with the Virtuoso Advanced-Node Platform, customers can achieve an improvement in custom physical design throughput versus traditional non-structured design methodologies, while maintaining a similar effort and cycle time via the advanced capabilities in the Virtuoso and Spectre tools.

Cadence delivered several custom/analog enhancements specifically to support the TSMC 5nm and 7nm+ process technologies. For example, Cadence introduced an accelerated custom placement and routing methodology, which enables customers to improve productivity and meet their power, multiple patterning, density and EM requirements. In addition, Cadence introduced universal poly grid snapping, asymmetric coloring support and voltage-dependent rule support for power/ground rails specifically for the 5nm process.

5nm and 7nm+ Library Characterization Tool Flow

The Virtuoso Liberate Characterization Solution and the Virtuoso Variety Statistical Characterization Solution have been validated to deliver Liberty libraries including advanced timing, noise and power models. The solutions utilized innovative methods to characterize Liberty Variation Format (LVF) models, enabling accurate process variation signoff for low-voltage applications and the ability to create EM models enabling signal EM optimizations and signoff.

“Using the latest design rules and PDKs, our customers have started designing complex SoCs on our most advanced process technologies,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Through the continuation of our collaboration with Cadence, we’ve certified their tools and flows for 5nm and 7nm+ designs, which can enable our customers to achieve their design goals within a fast, predictable timeline.”

“Over the past few years, Cadence has taken on a broader role in facilitating advanced-node adoption due to the optimizations and performance improvements across our digital and signoff and custom/analog tool suites,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “We’ve expanded our collaboration with TSMC by developing tools and flows that support their 5nm and 7nm+ process technologies, and our latest TSMC certifications are enabling us to support customers using the most advanced process nodes.”

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