Spin Transfer Technologies Announces Breakthrough MRAM Technology for SRAM and DRAM Applications

– Precessional Spin Current™ Structure Provides 40-70 Percent Boost to Spin-torque Efficiency of Any pMTJ — Improving Data Retention by Over 10,000 Times While Reducing Write Current –

April 30, 2018 -  FREMONT, Calif. – Spin Transfer Technologies, Inc., the leading developer of advanced STT-MRAM for embedded SRAM and stand-alone DRAM applications, today announced results of its unique Precessional Spin Current (PSC™) structure. The results from advanced testing of the PSC structure confirm that it will increase the spin-torque efficiency of any MRAM device by 40-70 percent — enabling dramatically higher data retention while consuming less power. This gain translates to retention times lengthening by a factor of over 10,000 (e.g., 1 hour retention becomes more than 1 year retention) while reducing write current. Improved efficiency is critical for enabling MRAM to replace SRAM and DRAM in mobile, datacenter and AI applications, as well as for improving retention and performance in high-temperature automotive applications. The company reported these results at the prestigious Intermag 2018 Conference.

Spin-torque efficiency is one of the core performance metrics of the pMTJ (perpendicular magnetic tunnel junction — the “bit” that stores the memory state in an MRAM memory) and is defined by the ratio between the thermal retention barrier, measuring how long data can be reliably stored in the memory, and the switching current necessary to change the value of the bit. In previous MRAM implementations, increasing the energy barrier to increase retention would require a proportional increase in write current — leading to higher power consumption and much faster wear-out of the pMTJ devices (lower endurance). The PSC structure is a breakthrough because it effectively decouples the static energy barrier that determines retention from the dynamic switching processes that govern the switching current. As a result, when the PSC structure is added to any pMTJ, benefits include:

  • A higher energy barrier when the pMTJ does not have current flowing through it, which is ideal for retaining data for long periods
  • An increased spin polarization when current is flowing and the device is writing a new state, which is ideal for minimizing switching current and extending the life of the device by many orders of magnitude

The PSC structure was designed from the outset to be modular and fabricated with any pMTJ — either the company’s own pMTJs, or a pMTJ from other sources. The PSC structure is fabricated during the pMTJ deposition process and adds approximately 4nm to the height of the pMTJ stack. The structure is compatible with a wide range of standard MRAM manufacturing processes, materials and tool sets — enabling any foundry to readily incorporate the PSC structure into existing pMTJ stacks without adding significant complexity or manufacturing costs.

“MRAM is attracting a lot of attention as an embedded memory for ASICs and MCUs, but issues of write current and data retention have caused concern,” said Jim Handy, general director of Objective Analysis. “Spin Transfer Technologies’ new PSC structure shows a lot of promise to solve a number of those issues and pave the path for MRAM to take a significant share of the embedded memory market.”

Spin Transfer Technologies’ testing of the PSC structure involved comparing the performance of the same pMTJ devices with and without PSC for a large number of devices within CMOS test chip arrays at various temperatures and device diameters. The tests exhibited a robust performance advantage due to the PSC structure, both during writing of the low-resistance (“0”) and the high-resistance (“1”) memory states. Some specific examples of the advantages that the data have shown are as follows:

  • Increase of the spin-torque efficiency by up to 70 percent
  • Demonstration of the efficiency gain across a range of sizes (40-60nm) and temperatures (30°C to 125°C)
  • Increase of the thermal energy barriers by 50 percent corresponding to an increase in data retention time of greater than four orders of magnitude while reducing the switching current
  • Reduction of read disturb error rate up to five orders of magnitude

These advantages have come without degradation to other performance parameters. The data for the PSC structure indicate significant potential for enabling high-speed applications as well as high-temperature automotive and other applications. Furthermore, since the data shows that the PSC structure’s efficiency gains actually increase as the pMTJ get smaller, the PSC structure opens new pathways to achieving embedded SRAMs in the latest 7nm and 5nm generations.

“There is a huge demand for a memory with the endurance of SRAM, but with higher density, lower operating power and with non-volatility. We believe the improvements the PSC structure brings to STT-MRAM technology will make it a highly attractive alternative to SRAM for these reasons,” said Mustafa Pinarbasi, CTO and SVP of Magnetics Technology at Spin Transfer Technologies. “We are excited to enable the next generation of STT-MRAM and to shake up the status quo of the memory industry through our innovation.”

About Spin Transfer Technologies

Spin Transfer Technologies, Inc. develops STT-MRAM technologies that combine advanced magnetics technologies, circuits, and memory architectures to create the industry’s lowest-cost, highest-performance STT-MRAM memories. The company’s disruptive STT-MRAM solutions aim to replace embedded SRAM and DRAM. The company was established by Allied Minds and New York University. For more information, please visit  www.spintransfer.com.


Contact:

Justin Gillespie
The Hoffman Agency
(925) 719-1097




Review Article Be the first to review this article
Aldec


Latest Blog Posts
Michelle Mata-ReyesAldec Design and Verification
by Michelle Mata-Reyes
ARM-based SoC Co-Emulation using Zynq Boards
Jobs
Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
Senior Software Architect Internet for EDA Careers at San Jose, California
Salesforce Technical Lead   East Coast  for EDA Careers at Cherry Hill, New Jersey
Sr. Application Engineer for Mentor Graphics at Fremont, California
Hardware Engineer, Board Design for Arista Networks at Santa Clara, California
Upcoming Events
DVCon U.S. 2020 at DoubleTree Hotel San Jose CA - Mar 2 - 5, 2020
OFC 2020 - The Optical Networking and Communication Conference & Exhibition at San Diego Convention Center San Diego CA - Mar 8 - 12, 2020
DATE '2020 at ALPEXPO Grenoble France - Mar 9 - 13, 2020
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 22 - 26, 2020



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise