Complimentary Superbug Risk Assessment Provided to DAC Attendees
SAN JOSE, Calif. — (BUSINESS WIRE) — June 14, 2018 — Oski Technology, Inc., the established and trusted leader in formal verification methodology and expertise, will host case studies from Cavium, Cisco, Nvidia, Qualcomm, and other clients in the Oski booth #2319 and partner booths at the Design Automation Conference (DAC) June 25-27, at Moscone West Center, San Francisco. These presentations will demonstrate how Oski Formal™, a unique Application-Specific Formal Verification Methodology, was used to uncover simulation-resistant superbugs to reach predictable verification sign-off. Among topics discussed will be cache coherence, system-level deadlock, and architectural formal verification. Theater seating is limited so pre-registration is encouraged. For full details and registration visit the Oski web site at http://www.oskitechnology.com/oski_dac.
Superbug Risk Assessment at DAC
The stumbling of Moore’s Law has led to the rise of simulation-resistant superbugs affecting a wide range of design domains including CPUs, GPUs, networking, wireless, functional safety, machine learning and artificial intelligence (AI). These superbugs are often application-specific and nearly impossible to detect using traditional methods. Oski will provide attendees a complimentary Superbug Risk Assessment to identify and rank simulation-resistant superbug vulnerabilities in their designs. These assessments will help managers and design teams determine the best verification strategy to eliminate superbugs without delaying time-to-market. Assessments will be done in a private suite under NDA to ensure design feature privacy. To schedule time with an Oski expert, visit http://www.oskitechnology.com/DAC-superbug-risk-assessment.
More Ways to Learn About Oski Formal at DAC
Designers can learn more about how Oski Formal is used to restore verification sign-off predictability.
Mentor Verification Academy
Presentation: “Superbugs: Leveraging Formal Verification to Combat Simulation Resistant Bugs”
Date/Time: June 26, 4:00 PM
Location: Mentor Verification Academy booth #1622 Level 1
Presentation: Architectural Formal Verification of a Coherency Manager
Date/Time: June 25, 10:30 AM
Location: Cadence booth #1308 Level 1
Designer Track Poster
Title: “Architectural Formal Verification of a Cache Coherence Manager”
Presenter: Nvidia, Oski Technology
Date/Time: June 26, 5:00 PM to 6:00 PM
Location: Level 2 Moscone West
Designer Track Session
Title: “Formal Sign-off Meets Real-World Tape Out Schedules”
Presenters: Oski Technology, Qualcomm
Date/Time: June 27, 4:30 PM to 6:00 PM
Location: Room 2012 Level 2
For more information about Oski’s ability to solve critical verification challenges, go to:
About Oski Technology
Oski Technology established itself as the unsurpassed trusted global leader in the domain of Formal Verification methodology and expertise. Founded in 2005, Oski serves six out of the top seven semiconductor design companies. Leaders in consumer electronics, communications, computing, image processing, data storage, research, defense, education, automotive, and medical turn to Oski to accelerate their verification process and produce higher quality designs than simulation alone allows. Oski has assembled the world’s largest dedicated team of experts that draws on hundreds of man-years of collective experience to provide Oski-certified verification sign-off. Oski reset the benchmark for formal verification with innovations such as its Formal Sign-off™ methodology, End-To-End Formal™ checkers and Oski Abstraction Models™. Oski's publications, training sessions and events, such as the Decoding Formal Club™, are recognized industry-wide as valuable resources of formal applications knowledge.
The Oski logo, Oski Formal, Decoding Formal Club, End-to-End Formal, Formal Sign-off, and Oski Abstraction Models are trademarks of Oski Technology. All other marks are the property of their respective owners.
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