CCIX™ Consortium Enables Next Generation Compute Architectures with the Availability of Base Specification 1.0

Specification Release Allows Companies to Deliver CCIX Production Devices

BEAVERTON, Ore. — (BUSINESS WIRE) — June 18, 2018 — The CCIX™ Consortium today announced the release of the CCIX Base Specification 1.0. The CCIX specification enables a new class of high performance, low latency cache coherent interconnect for the next-generation cloud, artificial intelligence, big data, database and other datacenter infrastructures.

The exponential growth of data combined with the demand for scalable compute-intensive applications, require the development of new compute, networking and storage platforms. These platforms will utilize highly efficient heterogeneous computing architectures that combine general purpose compute and accelerators such as GPUs, FPGAs, Smart NICs, Persistent Memory and other domain-specific programmable devices.

The CCIX Base Specification 1.0 defines a chip-to-chip interconnect for seamless data sharing between compute, accelerators and memory expansion devices with cache coherent shared virtual memory. CCIX specification leverages the PCI Express®4.0 architecture and ecosystem while increasing the throughput to 25GT/s per lane. Moreover, the specification adds the ability to maintain cache coherency across devices from different providers, to address the high-performance needs of heterogeneous compute systems, while enabling seamless acceleration between them.

The overarching benefits of CCIX include autonomous data movement between processor cache and accelerator cache without software driver involvement and the enablement of Cache Coherent Shared Virtual Memory programming paradigm. These components together substantially simplify application development and increase data centers performance, efficiency and overall return on investment.

“The CCIX ecosystem is providing the industry with a flexible interconnect to deliver true peer processing in cache coherent topologies with improved performance over existing interconnect technologies,” said Gaurav Singh, CCIX Consortium chairman. “We are beginning to see the availability of the first products with support for the CCIX 1.0 specification and expect this strong adoption to continue growing with the availability of the production version of the specification.”

The Base Specification 1.0 is available today for all CCIX members. To join CCIX and start using the specification, visit

Join us at the International Supercomputing Conference (ISC’18), June 24-28, Frankfurt Germany. At the CCIX booth, number L-432, the CCIX organization will showcase several application demonstrations over CCIX enabled devices.

About CCIX Consortium, Inc.

CCIX Consortium was founded to enable a new class of interconnect-focused on emerging acceleration applications such as machine learning, network processing, storage off-load, in-memory database and 4G/5G wireless technology. The standard allows processors based on different instruction set architectures to extend the benefits of cache coherent, peer processing to a number of acceleration devices including FPGAs, GPUs, network/storage adapters, intelligent networks, and custom ASICs. CCIX simplifies the development and adoption by extending well-established data center hardware and software infrastructure. This ultimately allows system designers to seamlessly integrate the right combination of heterogeneous components to address their specific system needs. For more information, please visit

CCIX Consortium Member Quote Sheet

The below quotes are provided by CCIX Consortium members regarding the release of the CCIX Base Specification 1.0


“Scaling general-purpose CPUs alone won't be sufficient to meet the performance targets of future edge computing, and new approaches to accelerating applications are needed,” said Jeff Defilippi, senior product manager, Infrastructure Line of Business, Arm and CCIX Consortium treasurer. “As a key contributor to the first open CCIX Base Specification Rev. 1.0 release, Arm believes this innovative and collaborative approach to coherent heterogeneous acceleration is a significant step forward in delivering the performance needed for analyzing and processing data from billions of connected devices.”


“Cadence is actively involved with the CCIX Consortium, and ratification of the CCIX 1.0 specification demonstrates the momentum behind this important interconnect standard,” said Stan Krolikoski, fellow, strategic alliances at Cadence. “In collaboration with our ecosystem partners, CCIX allows us to enable high-performance, heterogeneous multi-processor/accelerator multi-chip systems. Cadence was one of the first to deliver IP for CCIX, and our integrated CCIX solution consisting of PHY, controller, drivers and verification IP enables faster system integration while reducing our customers’ design risk with silicon-proven IP. This allows our customers to accelerate product development for the server and smart NIC markets with high confidence.”


“The release of the CCIX base specification 1.0 is a key milestone for designers who are ready to deliver a new generation of high-performance, heterogeneous systems for cloud computing applications,” said John Koeter, vice president of marketing at Synopsys. “Synopsys has been a contributing member of the CCIX consortium since its inception and provides designers with complete, silicon proven CCIX IP solution that enables them to achieve multi-gigabit performance with cache coherency for data-intensive SoCs.”

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