Mentor extends support of tools and solutions for Samsung Foundry's 8LPP and 7LPP process technologies

WILSONVILLE, Ore., June 26, 2018 — (PRNewswire) — Mentor, a Siemens business, today announced it has enabled a wide range of Mentor verification tools and solutions for the latest versions of Samsung Foundry's 8LPP and 7LPP offerings. Mentor's Calibre® nmPlatform and Analog FastSPICE™ (AFS™) custom and analog/mixed-signal (AMS) circuit verification platforms are available for use in the verification and sign-off of production tapeouts for Samsung Foundry's innovative 8LPP and 7LPP process technologies.

Samsung Foundry's 7LPP is its first process technology to use an EUV lithography solution, while its 8LPP is a non-EUV solution that provides a best-in-class mix of power, performance and accuracy relative to processes introduced prior to the EUV era.

"Samsung Foundry continues to offer the most competitive range of process technologies in the industry," said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. "Our longstanding collaboration with Mentor ensures our mutual customers are not only able to sign-off their designs with the industry's golden Calibre solution, but can also optimize their designs to best leverage Samsung Foundry's process offerings."

Samsung Foundry has enabled the full suite of tools in the Calibre platform to ensure designers can achieve tapeout success quickly and confidently:

  • For final sign-off to Samsung Foundry, multiple Calibre nmDRC solutions are employed, including core DRC, Calibre MultiPatterning, and Calibre PatternMatching. Each solution is used for various physical verification steps to help design teams ensure design-rule clean designs -- even for the most advanced and complex process parameters.
  • The Calibre nmLVS tool helps design teams verify circuits and address the growing layout complexity requirements of advanced node designs. Calibre nmLVS is the front-end to any Samsung Foundry extraction flow.
  • The Calibre xACT platform addresses the technical challenges inherent in advanced nanometer design, including multi-patterning, FinFETs, local interconnect, higher complexity and tighter constraints. Its unique hybrid engine delivers field-solver accuracy essential for detailed 3D structures like FinFETs, plus the performance necessary to enable fast throughput of full-chip designs.
  • The Calibre PERC reliability platform employs a unique integrated analysis of both the physical layout and the netlist to automate complex reliability checks. The latest Samsung Foundry Calibre Design Kit releases additional checks to mutual customers to address ESD and latch-up reliability concerns.
  • The Calibre YieldEnhancer product's SmartFill and engineering change order (ECO)/timing-aware fill capabilities allow customers to control design planarity through multiple design changes across intellectual property (IP), blocks and the full chip. This helps ensure designs comply with manufacturing planarity requirements and meet tapeout schedules. The product also enables designers to implement layout enhancements (such as via optimization) to improve manufacturing success.
  • The Calibre LFD™ tool accurately models the impact of lithographic processes to predict "as-manufactured" layout dimensions, identifying potential lithographic issues and enabling designers to optimize yield and product reliability. New EUV models and recipes were created to support Samsung Foundry's advanced technology nodes. The LFD tool is based on Mentor's production-deployed solutions for process-window modeling, mask synthesis, optical proximity correction (OPC), and resolution enhancement (RET) – all of which are used by Samsung Foundry in the manufacture of the 8LPP and 7LPP offerings.
  • Further extending Samsung Foundry's DFM offering, the latest Samsung Foundry Calibre design kit releases expand on the Samsung Foundry DFM scoring and analysis solution (based on the Calibre YieldAnalyzer tool) to streamline the process of making tradeoff decisions such as via redundancy checking.

To enable system-on-chip (SoC) designers to complete circuit verification, physical implementation and IC test with confidence, the Mentor AFS platform is enabled in Samsung Foundry's device models and design kits. Mutual customers rely on the AFS platform to deliver nanometer SPICE accuracy while verifying analog, RF, mixed-signal, memory, and custom digital circuits faster than with traditional SPICE simulators.

"Mentor continues to lead the way in delivering sign-off solutions for all of Samsung Foundry's silicon processes," said Joe Sawicki, vice president and general manager of the Mentor Design-to-Silicon Division. "Samsung Foundry's pace of innovation is impressive, and we are proud to work with Samsung Foundry to enable our mutual customers to fully leverage Samsung Foundry's range of process technologies to deliver innovations that best suit our customers' market and business requirements."

Contact for journalists
Jack Taylor
Phone: (512) 560-7143; Email: Email Contact

Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world's most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Website:

Mentor Graphics, Mentor, and Calibre are registered trademarks, and Analog FastSPICE, nmDRC, nmLVS, xACT, PERC, and LFD are trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owner.

Cision View original content:

SOURCE Mentor, a Siemens business

Company Name: Mentor, a Siemens business

Review Article Be the first to review this article
DAC 2020

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
D2S Brings GPU Acceleration to Semiconductor Design and Manufacturing
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Software Engineer for EDA Careers at RTP, North Carolina
Upcoming Events
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise