Synopsys FineSim SPICE Cuts Analog Simulation Time by 3X

Latest Release Accelerates Verification of Large, Advanced-node Post-layout Analog Designs

MOUNTAIN VIEW, Calif., Oct. 23, 2018 — (PRNewswire) —

Highlights:

  • 3X performance advantage over existing solutions significantly reduces verification time
  • New RF-class analysis capabilities to support high-frequency analog circuits
  • Ideally suited for large noise-sensitive power management, data conversion, and SERDES designs

Synopsys, Inc. (Nasdaq: SNPS) today announced major advances in its FineSim® SPICE circuit simulator for analog design. The FineSim SPICE 2018.09 release includes innovative technology that speeds up simulation of leading-edge analog designs by 3X. This is especially beneficial for large analog designs containing a massive number of post-layout parasitic elements, which is prevalent in advanced-node designs. Additional FineSim SPICE enhancements include exceptional scalability in multi-CPU environments and RF-class analysis capabilities to accurately verify circuit transient and phase noise performance.

"The Gigabit-per-second I/O with sophisticated charge-pump circuits in our state-of-the-art BiCS FLASH 3D flash memory demand high performance and accurate analog circuit simulators," said Toshihiko Himeno, group manager of Design Technology Group 2, Design Technology Innovation Division at Toshiba Memory Corporation. "With FineSim SPICE 2018.09, we are able to gain on average 2X speed-up for transient and noise simulation of the analog circuits in our BiCS FLASH."

FineSim SPICE complements industry standard HSPICE® simulation to provide a range of accuracy and performance that is well-suited for large, high-speed analog circuits, including ADC, DAC, PMIC, PLL, and SERDES. New parallel-partitioning and matrix-solver technology, along with advanced multi-level Newton and RC reduction algorithms, enable breakthrough simulation performance on these traditionally challenging designs. For ease-of-use, FineSim SPICE directly accepts HSPICE netlist, SPICE models, and setup information, and it is tightly integrated with Synopsys' Custom Compiler custom layout tool.

"As analog designs grow in size, speed, and complexity, designers are demanding innovation in circuit simulation to significantly speed up verification while maintaining the utmost accuracy," said Michael Jackson, corporate vice president of marketing for the Design Group at Synopsys. "We continue to invest in new circuit simulation technology to improve productivity and provide a continuum of SPICE solutions that deliver superior speed and accuracy."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:

James Watts
Synopsys, Inc.
650-584-1625 
jwatts@synopsys.com

 

Cision View original content: http://www.prnewswire.com/news-releases/synopsys-finesim-spice-cuts-analog-simulation-time-by-3x-300735866.html

SOURCE Synopsys, Inc.

Contact:
Company Name: Synopsys, Inc.
Web: http://www.synopsys.com
Financial data for Synopsys, Inc.




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