NSCore Inc. Addresses the IoT market need for an NVM IP Solution in advanced process nodes using Hi-k Metal Gate with their Multi-Time Programmable (MTP) Non-Volatile Memory (NVM) IP Solution

FUKUOKA, Japan, Nov. 5, 2018 / — The Embedded Flash Memory (NVM) technology has been a key component of the MCU and the IoT marketplace of several generations of technologies. Despite a significant amount of R+D effort, there is not a commercially available Embedded Flash Solution with Floating Gate or SONOS cells in the 28nm and lower process nodes which utilizing Hi-k Metal Gate (HKMG). Access to a low cost NVM IP solution in these advanced technology nodes, 28nm and below, is needed in the IoT market. It will result in a significant increase in the number of applications, and market adoption for IoT chip designs.

To address this need, NSCore is developing a new bit-cell structure, “P-Channel Schottky Cell”, on HKMG. It will require NO additional processing steps and it is targeted to achieve 10K cycles of endurance.

NSCore’s 30+ patents the its ability to build NVM IP solutions without any additional layers in a standard digital process, enables it to provide this unique solution in the 28nm technology node and beyond. The recently announced strategic relationship with Spectral Design & Test will also enable NSCore to offer a Compiler version of their NVM IP. This feature will enhance the chip designer abilities to make design and physical layout trade-offs as they architecture new chip designs.

The overall targeted performance for this new NVM are: 10usec of program time, 10K cycles of endurance and over 10 years of retention.

Since the NSCore NVM solution does not require any additional processing steps in the standard logic process, it will be a low cost NVM IP solution. Also due to the planar nature of these advanced but non-FinFET process nodes, many industry experts expect them to be the workhorse technology nodes for all future IoT development activity, and NSCore is looking to play a significant role in this market.




Review Article Be the first to review this article
DAC 2020

 True Circuits: Ultra PLL

Featured Video
Editorial
More Editorial  
Latest Blog Posts
Modesto (Mo) CasasGlobal Business in EDA
by Modesto (Mo) Casas
The Contingent Purchase Order Reassures Buyer and Seller
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Meet the New Cylynt, Fighting Software Piracy Around the Globe
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Jobs
Senior Physical Design/Layout Engineer for EDA Careers at EAST COAST, California
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Digital Design ASIC Manager for EDA Careers at RTP, North Carolina
Upcoming Events
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020
Drive World Conference & Expo at Santa Clara Convention Center Santa Clara CA - Aug 11 - 13, 2020
TrueCircuits:



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise