RISC-V SoftCPU Contest Winners Demonstrate Cutting-Edge RISC-V Implementations for FPGAs

Contest sponsored by Google, Antmicro, Lattice Semiconductor and Microchip honors four winners for creating ultra-small and high-performance FPGA soft CPU implementations with the RISC-V ISA

BERKELEY, Calif. & SANTA CLARA, Calif. — (BUSINESS WIRE) — December 6, 2018 — Today at the RISC-V Summit, the RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), honored the winners of the RISC-V SoftCPU Contest for creating innovative FPGA based CPU implementations targeting the RISC-V ISA.

The winners of the contest include: Charles Papon with VexRiscv in 1st place, Antti Lukats with Engine-V in 2nd place, Changyi Gu with PulseRain Reindeer in 3rd place and Olof Kindgren with SERV for the Creativity prize.

Sponsored by RISC-V Foundation Founding Platinum members Google, Antmicro, Lattice Semiconductor and Microchip Technology, through its Microsemi subsidiary, the RISC-V SoftCPU Contest was launched to promote innovative vendor-independent, modular and reusable FPGA applications. The participants were challenged to build extremely small, extremely powerful, softcore RISC-V implementations, with additional points awarded for novel approaches to the implementation itself.

“The RISC-V ISA is ushering in a new era of innovation, empowering companies and designers around the world to develop a wide variety of implementations that solve today’s most complex design challenges,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation. “The RISC-V SoftCPU Contest showcased how embedded designers can easily experiment with RISC-V implementations on FPGAs, designing novel approaches even within a limited timeframe.”

The entries were assessed on multiple criteria, including size and performance. While each winning entry targets a different set of tasks, the highest scoring were designed to work well on both the 25K LUT Microsemi IGLOO™2 or SmartFusion™2, or the 5K LUT Lattice iCE40 UltraPlus™ parts. All scoring entries are compliant with the RV32I ISA. Notably, the smallest entry, Engine-V created by Antti Lukats, used as little as 306 x LUT4s in the ultra-low resource design.

Winners:

About RISC-V Foundation

RISC-V (pronounced "risk-five") is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 200 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. More information can be found at www.riscv.org.



Contact:

Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700
Email Contact




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