Industry Leaders Collaborate with Synopsys on Modeling Standards to Address Design Down to 2nm

Manufacturing Challenges and Need for Ultra-low Power Drive Extensions to Liberty and Interconnect Technology Standards

MOUNTAIN VIEW, Calif., Dec. 19, 2018 — (PRNewswire) —

Highlights:

  • Liberty extensions drive optimal implementation/QoR for ultra-low power applications
  • Extended parasitic extraction modeling for advanced process and device technologies
  • Collaboration with technology innovators drives modeling standards for 2nm and beyond
  • Technical advisory boards include Arm, NVIDIA, Qualcomm, TSMC, and others

Synopsys, Inc. (Nasdaq: SNPS) today announced that the Liberty Technical Advisory Board (LTAB) and Interconnect Modeling Technical Advisory Board (IMTAB) have ratified new modeling constructs to address timing and parasitic extraction challenges at process nodes down to two nanometers (nm). Mobile device requirements for ultra-low power and manufacturing challenges require new approaches to ensure the best accuracy at signoff while enabling design tools to optimize for the lowest power consumption. In addition, device architectures, mask, and patterning techniques at these nodes result in artifacts that must be modeled by new extensions in the interconnect technology file (ITF).

In power analysis, the Liberty standard has been enhanced to provide better insight into the assumptions use for computation of dynamic power values in the library models. Extraction modeling in the ITF file now addresses gate resistance for new device architectures, as well as patterning extensions on interconnect and trench contact structures.

"Through close collaboration with leading foundries and IDMs, we are able to keep modeling standards out in front of the next wave of advanced process nodes," said Jacob Avidan, senior vice president of engineering in Synopsys' Digital Group. "The latest modeling enhancements ratified by the Liberty and ITF technical advisory boards are essential to achieving timing and power requirements that allow our partners to bring the highest quality designs to market in the shortest time possible."

All LTAB/IMTAB proposals have been quickly incorporated into Synopsys' Fusion Design Platform to enable support for early technology adopters. Tools in the Fusion Design Platform include Design Compiler® synthesis, IC Compiler II place-and-route, StarRC® extraction, PrimeTime® signoff, and PrimePower power analysis.  

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contact:
James Watts
Synopsys, Inc.
650-584-1625
jwatts@synopsys.com

 

Cision View original content: http://www.prnewswire.com/news-releases/industry-leaders-collaborate-with-synopsys-on-modeling-standards-to-address-design-down-to-2nm-300768598.html

SOURCE Synopsys, Inc.

Contact:
Company Name: Synopsys, Inc., Liberty Technical Advisory Board (LTAB), Interconnect Modeling Technical Advisory Board (IMTAB)
Web: http://www.synopsys.com
Financial data for Synopsys, Inc., Liberty Technical Advisory Board (LTAB), Interconnect Modeling Technical Advisory Board (IMTAB)




Review Article Be the first to review this article
Aldec

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Virtual 2020 CEO Outlook Set for June 17
Colin WallsEmbedded Software
by Colin Walls
Multiple constructors in C++
Jobs
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Software Engineer for EDA Careers at RTP, North Carolina
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Upcoming Events
Sensors Expo & Conference at McEnery Convention Center 150 W. San Carlos Street SAN JOSE CA - Jun 22 - 24, 2020
Nanotech 2020 Conference and Expo at National Harbor MD - Jun 29 - 1, 2020
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise