LOUISVILLE, Colo., Feb. 19, 2019 (GLOBE NEWSWIRE) -- The 2019 Design and Verification Conference and Exhibition U.S. (
DVCon U.S.) begins next week, offering attendees the industry’s most comprehensive technical program focused on the design and verification of electronics systems. Sponsored by
Accellera Systems Initiative, the 31st annual DVCon U.S. will be held February 25-February 28 at the DoubleTree Hotel in San Jose, California.
Over the course of the four-day program attendees can choose from a broad selection of sessions including 39 in-depth technical papers, four tutorials, 25 posters, nine short workshops, two panels and an informative keynote address.
The conference begins on Monday with Accellera Day. Cliff Cummings kicks off the day with a full morning tutorial, “ Gain Valuable Insight into the Changes and Features that Are Part of the New IEEE 1800.2 Standard for UVM and How to Make the Most of Them.” An Accellera-sponsored luncheon will follow that will provide updates on Accellera activities, honor the 2019 Technical Excellence Award recipient, and feature a panel discussion on the future of the SystemC language. Monday afternoon will have six short workshops for attendees to choose from, followed by the opening of the exhibition and reception.
Tuesday begins with paper sessions on Formal Verification Methodologies, Verification Strategies I, and Analog/Mixed-Signal Verification, followed by the poster session. The keynote address, “ Thriving in the Age of Digitalization,” will be presented by Fram Akiki, vice president, Electronics & Semiconductor Industry for Siemens PLM Software. Tuesday afternoon there will be sessions on The Universal Verification Methodology (UVM), Applying Big Data to Verification, and Verification Strategies II.
There will be two panels on Wednesday: “ Verification and Compliance in the Era of Open ISA—Is the Industry Ready to Address the Coming Tsunami of Innovation?” and “ Deep Learning—Reshaping the Industry or Holding to the Status Quo?” Wednesday paper sessions include: Hybrid Verification Environments, Advancements in Clock Domain Crossing Verification, Applications of the new Portable Stimulus Standard, Power-Aware Design and Verification, Formal Verification Techniques, and Portable Stimulus Case Studies.
Thursday will have three morning tutorials followed by three afternoon short workshops. For a complete list of the topics and presenters on Thursday, visit the agenda.
In addition to the Accellera-sponsored luncheon on Monday, Mentor, A Siemens Business, will host the luncheon on Tuesday, “ A Tale of Two Technologies: ASIC & FPGA Functional Verification Trends.” Wednesday’s luncheon will be hosted by Cadence, “ Data-Driven Verification: Going Beyond Metrics to Efficiency,” and the luncheon on Thursday, “ Industry Leaders Verify with Synopsys,” will be hosted by Synopsys.
The DVCon Expo will be open Monday evening from 5:00-7:00pm and Tuesday and Wednesday from 2:30-6:00pm. There will be a reception each evening during the Expo.
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.
|For more information, please contact:|
|Nannette Jordan||Barbara Benjamin|
|MP Associates, Inc.||HighPointe Communications|
|Email Contact||Email Contact|