The roadshow will feature live demonstrations and presentations from RISC-V Foundation members, includes free admission
BERKELEY, Calif. — (BUSINESS WIRE) — February 21, 2019 — The RISC-V Foundation, a non-profit corporation controlled by its members to drive a new era of processor innovation via the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the 2019 “ Getting Started with RISC-V” roadshow in collaboration with the Linux Foundation. This series of free, one-day events will occur in market-moving cities across North America, China and EMEA and will showcase innovative RISC-V implementations from members of the RISC-V Foundation. These roadshows are targeted for engineers, technical managers, makers, designers, students and educators. The sessions will feature engaging presentations, live demonstrations and an opportunity to speak with RISC-V experts and other local RISC-V enthusiasts.
Registration is currently open for the North American tour, scheduled for April 2019, with the China and EMEA events planned for Q2 and Q4 2019, respectively. Additional details on those roadshows will be available on the riscv.org website in the coming weeks.
“We are seeing extraordinary, fast-paced growth in the RISC-V ecosystem. We want to accelerate the trajectory of this growth. These one day RISC-V roadshows are designed to help educate and create awareness of RISC-V,” said Martin Fink, interim CEO of the RISC-V Foundation and Executive Vice President and Chief Technology Officer at Western Digital. “Please join us and learn how RISC-V is revolutionizing the processor industry, by enabling innovation, from the industry leaders of RISC-V development.”
North America Roadshow
These half-day free events will occur from April 1-4 and feature RISC-V Foundation members Andes Technology, Antmicro, Dover Microsystems, Hex Five, Imperas, Microchip Technology, SiFive and Western Digital.
- Boston – Waltham: April 1 at the Conference Center at Waltham. Register here.
- Austin: April 2 at the Commons Conference Center. Register here.
- Irvine: April 3 at AV Irvine. Register here.
- San Francisco Bay Area: April 4 at Western Digital in Milpitas. Register here.
The full agenda for North America can be found here: https://riscv.org/getting-started-riscv-events/
This full-day event will occur in Q2 2019 and feature RISC-V Foundation members Andes Technology, CloudBEAR, Codasip, C-SKY, GreenWaves Technologies, Hex Five, Nervos, Nuclei System, NXP, PerfXlabs, SiFive, Syntacore, Tangram and UltraSoC.
This full-day event will occur in Q4 2019 and feature RISC-V Foundation members Andes Technology, CloudBEAR, Codasip, GreenWaves Technologies, Hex Five, Microchip Technology, Minres, SiFive, Syntacore, Trinamic and Western Digital.
Further details on the event can be found here: https://riscv.org/getting-started-riscv-events/.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. With support from the Linux Foundation, members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. More information can be found at www.riscv.org.
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700