LOUISVILLE, Colo., Feb. 21, 2019 (GLOBE NEWSWIRE) --
WHO: The 2019
Design and Verification Conference and Exhibition (DVCon) U.S.
WHAT: Will include “Verification and Compliance in the Era of Open ISA –– Is the Industry Ready to Address the Coming Tsunami of Innovation?,” a panel exploring the RISC-V instruction set architecture’s features, benefits and challenges for processor IP and SoC development.
WHEN: Wednesday, February 27, from 8:30 a.m. until 9:30 a.m.
WHERE: Oak/Fir Room, DoubleTree Hotel, San Jose, Calif.
Moderator Kevin Krewell, principal analyst at TIRIAS Research, will lead panelists in a discussion about the RISC-V open standard, including the dynamic of compliance and customization, and defining requirements for identifying restrictions to customization.
Senior Vice President of Sales and Support, North America
Andes Technology Corp.
CEO and Founder
Breker Verification Systems
President and CEO
Director of Marketing
Mentor, a Siemens Business
Dr. Raik Brinkmann
President and CEO
For the complete DVCon U.S. 2019 schedule, including a list of tutorials, short workshops, panels, sponsored luncheons and events, visit
https://dvcon.org/agenda. To view the videos from the DVCon U.S. 2018 Accellera Day tutorials, visit
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org
Follow DVCon at:
Twitter: @dvcon_us or #dvcon_us to comment
For more information, contact: