LOUISVILLE, Colo., Feb. 21, 2019 (GLOBE NEWSWIRE) --

WHO: The 2019 Design and Verification Conference and Exhibition (DVCon) U.S. 

WHAT: Will include “Verification and Compliance in the Era of Open ISA –– Is the Industry Ready to Address the Coming Tsunami of Innovation?,” a panel exploring the RISC-V instruction set architecture’s features, benefits and challenges for processor IP and SoC development.

WHEN: Wednesday, February 27, from 8:30 a.m. until 9:30 a.m.

WHERE: Oak/Fir Room, DoubleTree Hotel, San Jose, Calif.
Moderator Kevin Krewell, principal analyst at TIRIAS Research, will lead panelists in a discussion about the RISC-V open standard, including the dynamic of compliance and customization, and defining requirements for identifying restrictions to customization.

Panelists are:
Emerson Hsiao
Senior Vice President of Sales and Support, North America
Andes Technology Corp.

Adnan Hamid
CEO and Founder
Breker Verification Systems

Simon Davidmann
President and CEO

Neil Hand
Director of Marketing
Mentor, a Siemens Business

Dr. Raik Brinkmann
President and CEO
OneSpin Solutions

For the complete DVCon U.S. 2019 schedule, including a list of tutorials, short workshops, panels, sponsored luncheons and events, visit To view the videos from the DVCon U.S. 2018 Accellera Day tutorials, visit

About DVCon

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit

Follow DVCon at:
Twitter: @dvcon_us or #dvcon_us to comment

For more information, contact:
     Barbara Benjamin
     HighPointe Communications


Review Article Be the first to review this article

Try our TCB Experts

Featured Video
Senior Layout Engineer for EDA Careers at EAST COAST, California
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior and (less) Senior Design Verification Engineers for EDA Careers at San Jose and Austin, California
Principal Electronics Engineer Test-20004966 for Northrop Grumman Mission Systems at Falls Church,, Virginia
Staff Engineer Digital-20003075 for Northrop Grumman Mission Systems at Redondo Beach, California
Principal Circuit Design Engineer for Rambus at Chapel Hill, North Carolina
Upcoming Events
Embedded Vision Summit 2020 at Santa Clara Convention Center Santa Clara CA - May 18 - 21, 2020
Sensors Expo & Conference at McEnery Convention Center 150 W. San Carlos Street SAN JOSE CA - Jun 22 - 24, 2020
Nanotech 2020 Conference and Expo at National Harbor MD - Jun 29 - 1, 2020
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise