Excellicon Awarded Patent for Promotion of Timing Constraints available through Constraints Manager product

May 15, 2019 - Laguna Hills, CA                                                                        

Excellicon Inc. an innovative provider of end-to-end timing constraints and clock analysis products announced award of patent for its innovative technique for promotion of timing constraints.

The Constraints Manager (ConMan) product provides multiple options for development of timing constraints for the entire chip. Promotion of timing constraints for bottom-up design methodology where IP and its associated timing constraints are imported into the Excellicon constraints database, is essential in order to develop the sub-module or full chip level timing constraints. Using Excellicon product, this critical step which is generally performed manually, is now fully automated and can be accomplished in fraction of the time as compared to the manual effort.

Constraints Manager is a full discovery and generation tool to automatically generate timing constraints. The product is capable of generating timing constraints from pure HDL code (RTL or netlist) without any seed timing constraints, yet allows designers to provide IP level constraints provided by IP vendors or perhaps from previous design versions. Constraints manager provides various techniques to incorporate and generate timing constraints for any layer of hierarchy. Users can use any of the three techniques to promote their timing constraints. First is the integration method often used for cases where the IP timing constraints continue to change, second isolation method where the timing constraints are selectively isolated as implied, and third is the In-Context technique for incremental propagation of timing constraints as defined and directed by designer.

Most of the propagation of constraints today is done using manual methods of manipulating hierarchy delimiters. This technique increases the risk of error introduction and missed constraints during the editing process. The available tools in the market simply add a layer of checking for assurance that adds additional work for designer to ensure the work is done properly. Excellicon multi-propagation capabilities not only automates the process, savings weeks of designer manual editing, but also provides a great deal of flexibility for designer to deal with any situation they may encounter as they attempt to generate proper top level constraints or produce lower level constraints from top level constraints which is often done for new design revisions.

“The patent award is an indication of lack of innovation in this space. We are pleased to have the opportunity to improve the design techniques available to designers.  Manipulating hierarchy delimiters for propagation of timing constraints, and more specifically promotion, is similar to use of cranks to start your car engine. This archaic approach often leads to many downstream issues where the timing closure becomes a huge challenge as each promoted path has to be properly checked given that the right context and use of right checks for validation often leading to erroneous results. The subject of the patent covers the unique technique where the timing constraints are promoted in the context of the entire chip through Excellicon constraints data base. Once the database has the necessary information the user can intelligently promote or demote timing constraints based on their requirements using any of the techniques provided in the Excellicon products.” said Peter Petrov, Excellicon’s CTO. 

About Excellicon

Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products Constraints Manager, Constraints Certifier, Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (EQ), and ConTree address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right!


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Rick Eram

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