Ausdia Expands Offices in Asia Pac Region to Support Customer Demand

New regional office meets growing demand for Timevision, the design constraint development solution that handles large, complex SoC designs

SUNNYVALE, Calif. — (BUSINESS WIRE) — May 20, 2019Ausdia, the leading provider of design constraints and verification solutions that complement timing signoff for complex system-on-chip (SoC) designs, has expanded its regional offices in India to support increasing customer demand for the company’s flagship product TimevisionTM. Pradeep CR has been appointed senior technical account manager at Ausdia’s new location in Bangalore, India.

“We are very fortunate to have Pradeep, with his technical, regional and industry knowledge, join our team and support the needs of our customers,” said Sam Appleton, CEO, Ausdia. “The expansion of our team reflects Ausdia’s commitment to our customers and our drive to address the continuing challenges of SoC designs.”

Pradeep will support customers in the Asia Pac Rim region. As account manager, he will support customers pre-and post sales. Prior to Ausdia, Pradeep was a staff applications consultant for Synopsys Design Methodology Solution (DMS) Products, chip-level static timing analysis (STA) lead at Microchip (Formerly PMC Sierra), lead application engineer at Extreme DA supporting GoldTime, field applications team supporting Mentor Graphics AMS suite (CoreEL Technologies) and Field Applications team supporting ASM assembly and fabrication product line.

Pradeep holds a bachelor’s degree in Electronics and Communications Engineering from Visvesvaraya Technological University and a master’s degree in VLSI System Design from Coventry University.

About Timevision Platform

Silicon design is becoming vastly more complicated and costly, and harder to design and verify. This is due to raw design size, increasing use of IP blocks, advanced technology nodes, number of clocks and clocked domains, and complexity of constraints to close timing across all combinations of corners and modes. There is a demand for a comprehensive product to generate and validate design constraints that correlate with static timing analysis engines to ensure design correctness. By using multicore software architecture, patented analysis algorithms, and innovative formal verification technology, the Timevision platform was developed to handle large, complex SoC designs (especially above 50M gates). Timevision integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run.

Ausdia will be showcasing the Timevision platform and the company’s latest technology advances at the upcoming Design Automation Conference (DAC), Booth 333, at the Las Vegas Convention Center in Las Vegas, Nevada from Sunday, June 2 to Thursday, June 6. Sign up today for a private demo at DAC.

About Ausdia

Ausdia Inc. is an experienced, trusted technology company solving design's toughest problems and transforming SoC design. The company is focused on delivering proven design constraint development and verification solutions that complement all implementation and timing signoff flows. The company’s groundbreaking approach represents a new way for SoC designers to enable massive productivity gains across the design flow resulting in shrinking design time which ultimately leads to a significant saving in design costs. Founded in 2006, Ausdia has a combined experience of over 60 years in EDA development, chip engineering and methodology. Ausdia is a privately-held company headquartered in Sunnyvale, California. For more information visit


Michelle Clancy, Cayenne Communication, Email Contact

Review Article Be the first to review this article

 Advanced Asembly

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
You’re Invited! SEMI’s Innovation for a Transforming World
intelThe Dominion of Design
by intel
The Long Game: Product and Security Assurance
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Setting a High Standard for Standards-Based IP
Sr Engineer - RF/mmWave IC Design for Global Foundaries at Santa Clara, California
Test and Measurement System Architect for Xilinx at San Jose, California
Business Operations Planner for Global Foundaries at Santa Clara, California
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
Upcoming Events
Innovation for a Transforming World -virtual Event at United States - Jul 13 - 14, 2021
DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021
SEMICON Southeast Asia 2021 Hybrid Event at Setia SPICE Convention Centre Penang Malaysia - Aug 23 - 27, 2021
7th International Conference on Sensors & Electronic Instrumentation Advances (SEIA' 2021) at Palma de Mallorca, Mallorca balearic islands) Spain - Sep 14 - 16, 2021
Verific: SystemVerilog & VHDL Parsers

© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise