Excellicon Introduces Automated Constraints Simulation to Minimize the Gate Level Simulation

May 21st, 2019 - Laguna Hills, CA -- Excellicon Inc. Leading and an innovative provider of end-to-end timing constraints products announced addition of latest capabilities to its product line up. SDC simulation is a new capability provided through the ConCert product by Excellicon. By enabling designers to perform simulation of timing constraints, the challenges often faced at late design stages can be addressed very early on through simulation of timing constraints at RTL stage of design.

Gate level sims which are typically performed upon completion of timing closure as the last step towards functional verification with respect to timing can now be performed at very early stages of the design by extracting SVA’s directly from the timing constraints which may have been either authored by designer, or IP providers, or even automatically generated by Excellicon’s Constraints Manager. This simulation capability ensures that timing requirements as described through timing constraints; SDC’s are functionally verified at very early design stages throughout the entire flow.

“Gate level simulation has always challenged designer and at times caught the designers by surprise very late in the design cycle. Being able to validate the timing requirements as they relate to the functional aspects of the design is a crucial step in verification. SDC simulation allows for designer to gain early insight into the functional implication of timing constraints, which in turn not only removes the uncertainties late in the game but also improves the coverage and quality of the design.” said Himanshu Bhatnagar, Excellicon’s CEO. 

About Excellicon

Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products Constraints Manager, Constraints Certifier, Exception-ToolBox (ET), Budgeting-Tool Box (BT), Equivalence-Checker (EQ), and ConTree address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right!

For further information contact:

Rick Eram

Email Contact



Read the complete story ...

Review Article Be the first to review this article

Featured Video
Latest Blog Posts
Graham BellSilvaco Nanometer Newsbyte
by Graham Bell
230 Power Device Simulations using Silvaco TCAD
Colin WallsEmbedded Software
by Colin Walls
Low power modes
Electrical Engineer ‐  ASIC Layout  for SECOND SIGHT MEDICAL PRODUCTS at Sylmar, California
Lead Validation Engineer for Alcon Research, LLC. at Johns Creek, Georgia
Principal Software Engineer (Middleware) for Alcon Research, LLC. at Lake Forest, California
Nano-Optics Process Engineer for DiCon Fiberoptics, Inc. at Richmond, California
Electrical Engineer for SECOND SIGHT MEDICAL PRODUCTS at Sylmar, California
Aerial Camera Operator for LeadAir, Inc. at Kissimmee, Florida
Upcoming Events
Embedded Systems Conference (ESC) Silicon Valley at San Jose Convention Center San Jose CA - Aug 27 - 29, 2019
Tech Symposium on RISC-V at Hotel Daniel Herzlia Tel Aviv Israel - Sep 5, 2019
PCB West 2019 at santa clara convention center Santa Clara CA - Sep 9 - 12, 2019
SEMICON Taiwan 2019 at TaiNEX Taipei Taiwan - Sep 18 - 20, 2019

Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise