Google and eSilicon at DAC 2019: Doing EDA in the Cloud? Yes, It’s Possible!

SAN JOSE, Calif., May 29, 2019 (GLOBE NEWSWIRE) -- Google and eSilicon will present eSilicon’s journey to ASIC and IP design in the cloud.

EDA in the Cloud? Yes, It’s Possible!
We often hear that the EDA industry is not yet ready for the cloud, usually due to objections about the nature of cloud-native technologies. However, the cloud seems like the ideal place to run chip designs: flexible compute resources available on demand, nearly infinite storage, and a pricing structure that avoids costs for idle resources. Some trailblazers in that space, like eSilicon, have realized this early on and embarked on a journey to the cloud to leverage its elasticity, performance, cost models and open the door to a new level of innovation in the EDA industry. Join us in this presentation to hear about that journey, the steps that were taken, the bumps along the road, and the building blocks that comprise this solution.

David Marshall — Enterprise Architect, Global IT, eSilicon Corp., San Jose, California
Guilhem Tesseyre — Customer Engineer Lead, Google, Inc., San Francisco, California

When & Where
Wednesday, June 5, 2019
2:00 PM - 2:45 PM
Design-On-Cloud Pavilion
DAC 2019
Las Vegas, Nevada

About DAC
The   Design Automation Conference (DAC 2019) is recognized as the premier conference for design and automation of electronic systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.

About e Silicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets.

Collaborate. Differentiate. Win.™

eSilicon is a registered trademark, and the eSilicon logo, neuASIC and “Collaborate. Differentiate. Win.” are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.


Sally Slemons Nanette Collins
eSilicon Corporation Public Relations for eSilicon
Email Contact Email Contact



Review Article Be the first to review this article

Featured Video
Latest Blog Posts
Graham BellSilvaco Nanometer Newsbyte
by Graham Bell
230 Power Device Simulations using Silvaco TCAD
Colin WallsEmbedded Software
by Colin Walls
Low power modes
Electrical Engineer ‐  ASIC Layout  for SECOND SIGHT MEDICAL PRODUCTS at Sylmar, California
Product Applications Engineer for DiCon Fiberoptics, Inc. at Richmond, California
Nano-Optics Process Engineer for DiCon Fiberoptics, Inc. at Richmond, California
Lead Validation Engineer for Alcon Research, LLC. at Johns Creek, Georgia
Principal Software Engineer (Middleware) for Alcon Research, LLC. at Lake Forest, California
Electrical Engineer for SECOND SIGHT MEDICAL PRODUCTS at Sylmar, California
Upcoming Events
Embedded Systems Conference (ESC) Silicon Valley at San Jose Convention Center San Jose CA - Aug 27 - 29, 2019
Tech Symposium on RISC-V at Hotel Daniel Herzlia Tel Aviv Israel - Sep 5, 2019
PCB West 2019 at santa clara convention center Santa Clara CA - Sep 9 - 12, 2019
SEMICON Taiwan 2019 at TaiNEX Taipei Taiwan - Sep 18 - 20, 2019

Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise