PCI-SIG® Achieves 32GT/s with New PCI Express® 5.0 Specification

The organization doubles PCI Express 4.0 specification bandwidth in less than two years

BEAVERTON, Ore. — (BUSINESS WIRE) — May 29, 2019PCI-SIG® today announced the release of PCI Express® (PCIe®) 5.0 specification, reaching 32GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations.

“New data-intensive applications are driving demand for unprecedented levels of performance,” said Al Yanes, PCI-SIG Chairman and President. “Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the foreseeable future.”

“For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software,” noted Nathan Brookwood, research fellow at Insight 64. “Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow2. We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly.”

PCIe 5.0 Specification Highlights

  • Delivers 32 GT/s raw bit rate and up to 128 GB/s via x16 configuration
  • Leverages and adds to the PCIe 4.0 specification and its support for higher speeds via extended tags and credits
  • Implements electrical changes to improve signal integrity and mechanical performance of connectors
  • Includes new backwards compatible CEM connector targeted for add-in cards
  • Maintains backwards compatibility with PCIe 4.0, 3.x, 2.x and 1.x

The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking.

To learn more about the PCIe 5.0 specification, visit www.pcisig.com. PCI-SIG members can download the full specification here.

About PCI-SIG

PCI-SIG is the consortium that owns and manages PCI specifications as open industry standards. The organization defines industry standard I/O (input/output) specifications consistent with the needs of its members. Currently, PCI-SIG is comprised of over 700 industry-leading member companies. To join PCI-SIG, and for a list of the Board of Directors, visit www.pcisig.com.

PCI-SIG, PCI Express, and PCIe are trademarks or registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

Supporting Quotes for PCIe 5.0 Specification

AMD

“AMD congratulates PCI-SIG on the release of the PCI Express 5.0 specification to the industry and the future 2x increase in performance it is expected to deliver. We expect to bring our first PCIe 4.0 specification CPUs to market this year and look forward to meeting the future bandwidth demands of end-users with PCIe 5.0 technology.”

~Gerry Talbot, AMD Corporate Fellow, Technology & Engineering Group, AMD

Astera Labs

“Completed in under 2 years, PCI Express 5.0 technology is poised to quickly become the connectivity backbone in the next generation of servers. Astera Labs, a provider of innovative connectivity solutions, supports the new technology and emerging heterogeneous compute topologies with purpose-built signal conditioning products that enable robust PCIe 4.0 and PCIe 5.0 interconnects.”

~Sanjay Gajendra, Chief Business Officer, Astera Labs

Cadence

“PCI-SIG’s announcement of the PCI Express 5.0 specification is a significant step that addresses the increasingly demanding requirements for compute and networking applications. The doubling of bandwidth to 32GT/s can significantly reduce the I/O bottleneck and bolster overall application performance. As an ongoing contributor to the development of the PCI Express specification, Cadence supports this latest release with complete, high-quality PHY and controller IP, and verification IP including the TripleCheck verification technology. This comprehensive Cadence offering allows customers to get to market faster with a robust, high-performance solution while reducing development costs and risk.”

~Amjad Qureshi, Corporate VP, R&D in the IP Group at  Cadence Design Systems

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