Concept Engineering Accelerates Semiconductor Development With Improved Customizable Debugging Platform

Freiburg, Germany – May 31, 2019 – Concept Engineering, the leader in visualization and debugging technology for electronic circuits and systems, will unveil version 6.11 of the de facto industry standard Vision debugging platform at the Design Automation Conference (DAC), being held June 3 - 6, 2019 at the Las Vegas Convention Center, Las Vegas, NV.

Concept Engineering's Vision debugging platform consists of the following individual tools:

  • StarVision® PRO flagship tool which combines the debugging features of all individual Vision tools into one customizable mixed-signal and mixed-language tool.
  • RTLvision® PRO for easy RTL code exploration, integration, debugging and intellectual property (IP) development.
  • SpiceVision® PRO for advanced exploration and debugging features for transistor-level and post-layout debugging (SPICE-level).
  • GateVision® PRO for full chip gate-level netlist debugging of complex SoC netlists.

The Vision tools provide powerful debugging and advanced flow automation capabilities for the design of complex SoCs, ASICs, and mixed-signal chips.

New Vision Debugging Platform features are:

  • An increase in tool performance and robustness when working with the largest and most complex SoC designs developed today.
  • The GUI cockpit now offers a flexible split-screen mode, where the system displays two different design views, side-by-side, allowing more comfortable debugging and cross-probing.
  • A new infobox GUI window provides a comprehensive report for selected objects including a compact visual connectivity report.
  • GUI improvements for easy and more efficient parasitic netlist exploration.
  • GUI cockpit offers improved drag-and-drop functionality from other applications (for improved interaction with other tools and existing tool flows).
  • Option to perform more relaxed Verilog and VHDL design parsing to better support incomplete or unfamiliar complex designs.
  • Improved SPICE netlist parser can automatically select proper macro models so that unfamiliar designs can be explored quicker and easier.
  • The Verilog netlist exporter has been improved to better support simulation tool flows.
  • Automatic logic recognition for SPICE netlists has been improved. As a result more compact and easier to understand schematic diagrams will be generated and allow faster and easier inspection of SPICE netlists.

“We are dedicated to continue to offer our customers significant performance improvements year after year,” said Gerhard Angst, president and CEO of Concept Engineering.  “With version 6.11, our customers will benefit from improved GUI for smoother and more efficient design exploration and debug. Along with multiple improvements to support development of complex mixed language SoCs.”

The company's updated Vision platform, along with its visualization engines and libraries for EDA tool developers (NIview, T-engine and S-engine), will be demonstrated in the Concept Engineering booth #532 at DAC 2019.


Version 6.11 Vision tools can be downloaded after DAC 2019 from the company's website

About Concept Engineering

Concept Engineering is a privately-held company based in Freiburg, Germany, that provides visualization and debugging technology for electronic circuits and systems, including automatic schematic generation technology for all major design levels. The company's technology helps electronic design engineers to easily understand, debug, optimize and document electronic designs. Concept Engineering's software technology is used in many fields in the EDA market, including: RTL development, IP reuse, ASIC and SoC design, FPGA design, analog/mixed-signal design, logic synthesis, design verification, test automation, post-layout analysis, debugging and visualization at system-, RTL-, netlist- and transistor-level.

Editorial Contact:

Michelle Clancy,  Cayenne Communication, Email Contact

+1 503-702-4732

Read the complete story ...

Review Article Be the first to review this article
Featured Video
Latest Blog Posts
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automating UVM-Based IP and SoC Functional Verification
Harry FosterGuest Blogger
by Harry Foster
Calling All Data Scientists!
Quality Engineer for Novanta at Bedford, Massachusetts
Computer Engineer - Engineering Automation for Micron Technology, Inc. at Atlanta, Georgia
FPGA DESIGN for L3Harris at Burlington,, Canada
SIM COE - Engineering Automation for Micron Technology, Inc. at San Jose, California
Upcoming Events
LoRaWAN World Expo at Palais des Congrès Paris France - Jul 6 - 7, 2022
Design Automation Conference 2022 at Moscone West Center San Francisco CA - Jul 10 - 14, 2022
SEMICON West & FLEX Conference & Exhibition at Moscone Center San Francisco, CA - Jul 11 - 14, 2022
2022 International Test Conference at Disney Land Hotel Anaheim CA - Sep 26 - 29, 2022

© 2022 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise