Avery Design Systems Announces SimCluster GLS to Accelerate Gate-Level Sign-Off Simulations

TEWKSBURY, Mass. — (BUSINESS WIRE) — May 30, 2019 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of SimCluster GLS that performs gate-level parallel simulation to achieve 3-5X speed up of sign-off simulations.

“As chips get larger the feasibility of performing post-layout SDF-based gate-level simulation gets harder and harder,” said Chris Browy, VP Sales/Marketing. SimCluster GLS performs scalable parallel simulation using VCS, Xcelium, or Questa in either multi-core and datacenter cluster compute environments to simulate faster and shrink turn-around times on sign-off simulations.

Highlights of the new SimCluster GLS solution:

  • No design changes, no testbench changes, no SDF changes
  • Engines run with cycle-based or lock-step synchronization
  • Supports all three major simulators (Xcelium/VCS/Questa)
  • Simulation analyzer tool generates design block workload, port change activities, interconnect complexity between blocks, synchronization analysis, and design hierarchy report
  • Automatic coarse-grained partitioning of flat and hierarchical netlists
  • Patent pending methods further optimize performance

Visit us at the Design Automation Conference in Las Vegas during June 2-6.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, CXL, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.



Contact:

Avery Design Systems
Chris Browy, 978-851-3627
Email Contact




Review Article Be the first to review this article
Aldec

Featured Video
Latest Blog Posts
Graham BellSilvaco Nanometer Newsbyte
by Graham Bell
230 Power Device Simulations using Silvaco TCAD
Colin WallsEmbedded Software
by Colin Walls
Low power modes
Jobs
Principal Software Engineer (Middleware) for Alcon Research, LLC. at Lake Forest, California
Nano-Optics Process Engineer for DiCon Fiberoptics, Inc. at Richmond, California
Electrical Engineer for SECOND SIGHT MEDICAL PRODUCTS at Sylmar, California
Lead Validation Engineer for Alcon Research, LLC. at Johns Creek, Georgia
Electrical Engineer ‐  ASIC Layout  for SECOND SIGHT MEDICAL PRODUCTS at Sylmar, California
Product Applications Engineer for DiCon Fiberoptics, Inc. at Richmond, California
Upcoming Events
Embedded Systems Conference (ESC) Silicon Valley at San Jose Convention Center San Jose CA - Aug 27 - 29, 2019
Tech Symposium on RISC-V at Hotel Daniel Herzlia Tel Aviv Israel - Sep 5, 2019
PCB West 2019 at santa clara convention center Santa Clara CA - Sep 9 - 12, 2019
SEMICON Taiwan 2019 at TaiNEX Taipei Taiwan - Sep 18 - 20, 2019



Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise