True Circuits Demonstrates Silicon Proven DDR 4/3 PHY at the Design Automation Conference

Verified at 3200Mbps in TSMC 28nm HPC+

June 3-5, 2019, Las Vegas Convention Center, Booth #553


True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries.


At the Design Automation Conference (DAC), True Circuits will showcase its high performance, silicon proven DDR 4/3 PHY hard macro with state-of-the-art tuning and training, and remarkable physical flexibility to adapt to each customer’s die floorplan and package. The DDR 4/3 PHY has been developed using the powerful custom design automation tools that have made TCI’s line of high performance PLLs and DLLs a staple in the semiconductor industry for over 21 years.  The availability of this silicon proven PHY means customers can now license a PHY with significant performance and features without all the implementation and timing closure hassles that are common with current DDR offerings.

The DDR 4/3 PHY has the following key characteristics and benefits to customers:

  • High performance
  • Low system cost
  • Simple to integrate
  • Easy timing closure
  • Automatic training
  • Simple to bring up

The DDR 4/3 PHY has been undergoing extensive silicon testing in our lab and the results, while early, are quite impressive.  On our DDR4 test boards with Micron memories and TSMC 28nm HPC+ test chips, the PHY is running at 3200Mbps without bit errors.  On our DDR3L test boards, the PHY is running at 1866Mbps without bit errors.  Silicon testing is ongoing and leverages TCI’s highly automated and well proven test infrastructure and test methodologies.  Testing includes functional write/read tests across PVT on five silicon corners, silicon based verification of PHY training, evaluation of training results from delay timing and Vref margin tests, and automated scope-based verification of system signal integrity.  Testing will conclude with compliance tests and final silicon reports.

TCI went to great lengths to implement the DDR 4/3 PHY test chip just as our customers would implement a product chip.  We used industry standard tools to synthesize, place and route the test chip, incorporated a Northwest Logic controller and Aragio Solutions DDR and General Purpose IOs, utilized custom high quality test boards and sockets, and used Micron memories. Taking this approach allowed us to experience and evaluate every aspect of the implementation of the PHY so we can better support our customers.

“TCI set out to develop a DDR PHY that addresses many of the shortcomings and inconveniencies of existing DDR offerings in the market.  After years of dedication and exemplary engineering, our team has verified the TCI DDR 4/3 PHY operates at 3200Mbps in DDR4 mode on 28nm silicon, and equally impressive, the PHY worked right out of the box”, remarked John Maneatis, True Circuits’ President.  “We are now in a confident position to continue with our 16nm and 7nm PHY porting efforts and fully engage with customers who seek a real alternative to the market status quo.”

During the show, we will be giving short presentations and demos of the PHY in action. This will be a great opportunity to ask questions and learn what makes the TCI DDR 4/3 PHY hard macro one special piece of IP.

We will also feature our complete line of standardized and silicon-proven general purpose, clock generator, deskew, spread spectrum, Ultra and IoT PLLs, and multi-slave and multi-phase DLLs that spans nearly all performance points, features and foundry processes typically requested by ASIC, FPGA and SoC designers. These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications.  They are pin-programmable, highly process tolerant, reusableand available for delivery in TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 6nm.  We recently added support for the GLOBALFOUNDRIES 12nm LP process, so we have all your timing needs covered.

As always, we are glad to discuss your IP needs, including IP selection, IP integration, IP reuse, jitter specifications and silicon testing, so please stop by our booth #553 and spend some time with the timing experts!                                                                                                                 

You may also want to check out a recent article by John Maneatis, Ph.D., True Circuits' President, who offers an insightful response to an article posted on which touted the merits of digital PLLs and the demise of analog PLLs. John is widely regarded as a pioneer in the development of PLLs and related timing circuits, and over the last 25 years, he and our engineering teams have developed a lot of innovative PLL technology. With each process technology generation, the preferred mix of analog and digital circuitry has changed and they have addressed the challenges with a variety of architectures. In this article, John outlines the advantages and disadvantages of synthesizable-digital PLLs/DLLs and makes a strong case for hardened mixed-signal designs as created by the well proven TCI approach that maximizes design efficiency, porting and reuse of analog/mixed-signal PLLs and produces high-performance, pin programmable designs that meet a wide range of operating requirements without the need for customer tweaking and the resulting headaches. 

When and Where

Las Vegas Convention Center, Las Vegas, NV

True Circuits Booth #553                          

Monday - Wednesday, June 3-5, 9:00 AM to 6:00 PM

Presentations and live demonstrations will be given throughout each day of the conference.


For more information about True Circuits' PLLs and DLLs, please visit

For more information about the Design Automation Conference, please visit

About True Circuits DDR PHYs

The DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Automatic training is included for multi-cycle write leveling and read gate timing, read/write data eye timing, and PHY Vref and DRAM Vref settings.

The PHY employs a localized and optimized PHY-to-memory controller interface to ease timing closure. The circuitry in each pin is able to measure the data eye and jitter, and calculate flight delays. The PHY also includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data.

Remarkable physical flexibility allows the PHY to adapt to each customer’s die floorplan and package constraints, yet is delivered and verified as a single unit for easy timing closure with no assembly required. The PHY is DFI 4.0 compliant, and when combined with a suitable DDR memory controller, a complete and fully-automatic DDR system is realized.

The True Circuits DDR 4/3 PHY hard macro is immediately available for customer delivery in TSMC's 28nm HPC/HPC+ process. The PHY will be available in additional TSMC and GLOBALFOUNDRIES processes in the very near future.  Interested customers can obtain more product information on the web at by contacting True Circuits at

About True Circuits IoT PLLs

The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power.  It has a wide frequency range with multiplication factors up to 8192, allowing the PLL to run off of a small and inexpensive 32KHz crystal and still clock a 32-bit CPU at up to 250MHz.  It is ideal for IoT applications like wearables and sensor devices, where the power-performance profile must be managed tightly, and possibly over a very wide frequency range.

About True Circuits Ultra PLLs

The Ultra PLL employs a new state-of-the-art architecture and uses high-speed digital and analog circuits to achieve exceptional performance, with many useful features.  It has ultra-low jitter (<500fs) for the most demanding SerDes and ADC input clocks. It has ultra-wide frequency range with multiplication factors from 3 to over 250,000, supporting reference clocks as low as 32KHz.  It also has precise frequency control with at least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution.  It can even generate precise and adjustable frequency spreading with programmable rate and depth to meet tight FCC requirements.  The Ultra PLL packs all these features into a compact size that draws low power and, with full pin programmability, one PLL can be used for all applications on a SoC.

About True Circuits PLLs and DLLs

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