Astera Labs Verifies Its System-Aware PCI Express® 5.0 Smart Retimer Using Avery Design Systems PCIe® 5.0 Verification IP

TEWKSBURY, Mass. — (BUSINESS WIRE) — June 18, 2019 — Avery Design Systems, leader in functional verification solutions today announced that Astera Labs successfully utilized Avery's Peripheral Component Interconnect PCI Express® (PCIe®) 5.0 Verification IP and services to verify its breakthrough system-aware PCIe 5.0 Smart Retimer.

The Avery PCIe 5.0 VIP supports models and testsuites for the newly ratified PCI 5.0 specification including latest enhancements for retimers operating at 32 GT/s and the alternate protocol mode of operation.

“At Astera Labs, our priority is to deliver Smart Retimer products that fully meet PCIe specification and achieve plug-and-play interoperation,” said Jitendra Mohan, chief executive officer at Astera Labs. “Avery PCIe 5.0 VIP is a critical tool in our verification environment to thoroughly test our design and deliver a high quality product to our customers.”

“The PCIe 5.0 specification delivers unprecedented performance levels at 32 GT/s while extending reach of I/O system topologies and breadth of solutions spanning HPC to mobile/IoT applications,” said Al Yanes, PCI-SIG chairman and president. “The PCIe verification ecosystem space is so crucial to our members, as it helps them to develop chips and systems with highest quality, interoperability, and compliance.

About PCI-SIG
PCI-SIG is the consortium that owns and manages PCI specifications as open industry standards. The organization defines industry standard I/O (input/output) specifications consistent with the needs of its members. Currently, PCI-SIG is comprised of over 800 industry-leading member companies. To join PCI-SIG, and for a list of the Board of Directors, visit  www.pcisig.com.

About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, CXL, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.



Contact:

Avery Design Systems
Chris Browy, 978-851-3627
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