StreamDSP Announces Major Update to 17.3 IP Core

StreamDSP has added support for multiple FPGA families to the 17.3 (sFPDP Gen 3) IP core.

We expect the adoption of VITA 17.3 to accelerate over the next few years and we’re actively working on new enhancements and features. It’s an exciting time to be in the communications IP business!

“We’re excited to support 100G links using only 4 physical lanes,” said Greg Schueller, Director of Business Development, StreamDSP. “The industry continues to demand higher bandwidth for applications such as radar and signal processing, and the new VITA 17.3 standard is performing a key role here,” said Greg. “We expect the adoption of VITA 17.3 to accelerate over the next few years and we’re actively working on new enhancements and features. It’s an exciting time to be in the communications IP business,” added Greg.

The recently approved VITA 17.3 specification, also known as Serial Front Panel Data Port (sFPDP) Gen 3, is a next-generation communications protocol designed as the successor to VITA 17.1. VITA 17.3 improves link efficiency and bandwidth by using the same 64B/67B encoding technology found in newer protocols such as Interlaken and Serial RapidIO Gen 3, and also supports multi-lane channel bonding to allow for maximum bandwidth scalability. Like VITA 17.1, VITA 17.3 supports both framed and unframed data types and is designed to easily interface to existing systems. VITA 17.3 is ideal for low-latency remote sensor applications, FPGA chip-to-chip interfaces, FPGA optical interfaces, and backplane interconnect. The VITA 17.3 specification allows operation at any line rate and number of channels, making it a highly scalable solution.

The StreamDSP sFPDP Gen 3 IP core is a fully-compliant implementation of the VITA 17.3-2018 standard. To allow for system upgrades, StreamDSP was able to keep the user interface to the sFPDP Gen 3 IP core virtually the same as their current (and very popular) 17.1 IP core.

With the v1.8 release, the StreamDSP sFPDP Gen 3 IP Core now supports the following FPGA devices:

  • Altera Stratix-IV GX
  • Altera Stratix-V GX
  • Intel Cyclone-10
  • Intel Arria-10
  • Intel Stratix-10 (L-Tile and H-Tile)
  • Xilinx Virtex-6 LXT
  • Xilinx Artix-7
  • Xilinx Kintex-7
  • Xilinx Virtex-7 GTX
  • Xilinx Virtex-7 GTH
  • Xilinx Kintex UltraScale
  • Xilinx Virtex UltraScale
  • Xilinx Zynq UltraScale Plus
  • Xilinx Kintex UltraScale Plus
  • Xilinx Virtex UltraScale Plus

In addition to the devices listed above, StreamDSP is committed to adding support for ANY transceiver based FPGA family with a valid request.

StreamDSP provides “ready-to-run” simulations and reference designs targeted to popular development boards for each of the supported FPGA families. Unlike many other vendors, StreamDSP offers free time-limited evaluations with full technical support. This allows StreamDSP’s customers to quickly and easily verify proper operation both in simulation and also with their chosen device family to minimize integration time and reduce risk. The wide range of FPGA device support also allows StreamDSP to do extensive compatibility testing between different FPGA families to ensure error-free communications between all FPGA families. The sFPDP Gen 3 IP core from StreamDSP makes it simple for customers to connect Intel/Altera and Xilinx devices together with very high bandwidth connections.


StreamDSP LLC, 20 S Third St, Suite 210, Columbus, OH, 43215, USA

More information about the Serial FPDP VITA 17.3 Standard can be found at

For more specific information about StreamDSP’s IP products, please visit:, or call (855) 377-3742.

About StreamDSP LLC

StreamDSP is an intellectual property (IP) company specializing in video, serial communications, and data storage solutions for Field Programmable Gate Array (FPGA) devices. Headquartered in Columbus, OH, StreamDSP has over 50 years of combined experience serving the military and commercial markets, and is focused on developing IP and providing custom design services for FPGAs.


Greg Schueller
Director of Business Development
+1 (855) DSP-FPGA 

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