OneSpin Addresses the Challenges of RISC-V Verification Through Series of Speaking Engagements, Workshop, and Tutorials

Series designed to help developers and integrators effectively verify RISC-V integrity: functional correctness, safety, security, and trust

MUNICH — (BUSINESS WIRE) — September 16, 2019OneSpin® Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure, and trusted integrated circuits, today announced several technical speaking public engagements focused on the verification of RISC-V processor cores. The series of presentations, workshops, and tutorials will educate developers and integrators of RISC-V processor cores on how to properly address the challenges associated with verifying these cores and meeting ISA compliance.

OneSpin will present at the following events kicking off September 16 through October 29, 2019:

RISC-V EMEA Roadshow
Tel Aviv, Israel – September 16
Munich, Germany – September 18
London, UK – September 26

Verifying the Full Scope of RISC-V Integrity

This talk presents a verification flow covering the full scope of integrity for RISC-V cores and SoCs, spanning functional correctness, safety, security, and trust. It is essential for RISC-V core developers, engineers evaluating cores for possible use, and SoC teams integrating RISC-V cores from internal or external sources.

DVCon India
Bangalore, India – September 25

Effective Verification of RISC-V Cores and SoCs

This workshop provides guidance for RISC-V core vendors who need to verify their IP, developers of cores for internal consumption, engineers evaluating cores for possible use, and SoC teams integrating RISC-V cores from internal or external sources. Topics include formal verification of the ISA, detection of Trojans and malicious logic, and detection of hardware security holes.

RISC-V Week in Paris
Paris, France – October 2

Complete Formal Verification of RISC-V Cores for Trojan-Free Trusted ICs

RISC-V processor IPs are increasingly being integrated into system-on-chip designs for high-integrity, trusted applications. This presentation examines an efficient, novel, formal-based RISC-V verification methodology that detects both hardware Trojans and genuine functional errors present in the RTL code. The solution is demonstrated on an open-source RISC-V implementation using a commercially available formal tool.

DVCon Europe
Munich, Germany – October 29

RISC-V Integrity: A Guide for Developers and Integrators

The tutorial covers the complete scope of RISC-V core and SoC integrity: functional correctness (compliance to the ISA), safety, security, and trust. It includes examples of actual bugs found in open-source implementations of RISC-V cores and RISC-V-based SoCs.

For more information on how OneSpin can help with RISC-V verification, download the white paper " Assuring the Integrity of RISC-V Cores and SoCs."

About OneSpin Solutions

OneSpin Solutions is a leading provider of certified IC integrity verification solutions for building functionally correct, safe, secure, and trusted integrated circuits. These solutions are based on OneSpin's widely used formal verification technology and assure the integrity of SoCs, ASICs and FPGAs. Headquartered in Munich, Germany, OneSpin partners with leaders worldwide in automotive and industrial applications; defense; avionics; artificial intelligence and machine learning; consumer electronics; and communications. Its advanced solutions are well-suited for developing heterogeneous computing platforms, using programmable logic, and designing and integrating processor cores, such as RISC-V. OneSpin's customer-oriented commitment is fundamental to its growth and success. OneSpin: Assuring IC Integrity. Visit to learn more.

OneSpin, OneSpin Solutions and the OneSpin logo are trademarks of OneSpin Solutions GmbH. All other trademarks are the property of their respective owners.

Connect with OneSpin:

Twitter: @OneSpinSolution


Media contact US:
Michelle Clancy, Cayenne Communication
Tel.: 503.702.4732,

Media contact Europe:
Gabriele Amelunxen, PRismaPR
Tel.: +49 (0) 8106 - 24 72 33, Email Contact

Review Article Be the first to review this article

Featured Video
Senior Physical Design/Layout Engineer for EDA Careers at EAST COAST, California
Digital Design ASIC Manager for EDA Careers at RTP, North Carolina
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Upcoming Events
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020
Drive World Conference & Expo at Santa Clara Convention Center Santa Clara CA - Aug 11 - 13, 2020
ISS Europe at Brussels Belgium - Sep 1 - 3, 2020
Robotics Summit & Expo at Hynes convention center Boston MA - Sep 24 - 25, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise