Moortec, the go-to leaders of in-chip technologies will be showcasing their PVT Monitoring Subsystem IP at the 2019 TSMC Open Innovation Platform Ecosystem Forum at Santa Clara Convention Centre on Thursday, 26th September, 2019.
Moortec’s CEO, Stephen Crosher will also be presenting a paper entitled “The Challenges Posed by Dynamic Uncertainty on AI & ML Devices Targeting 16nm, 7nm & 5nm” during the OIP Forum multi-track technical sessions.
Visit booth #703 to discuss your embedded monitoring requirements with our expert team who can explain why this type of IP has become such a mandatory part of advanced node system design.
Moortec are proud to be full and active members of the TSMC IP Alliance program, a key component of TSMC Open Innovation Platform® (OIP). Being a TSMC IP Alliance member, Moortec can leverage TSMC’s advanced technologies with its high-performance analog IP and subsystem solutions. Moortec’s portfolio of PVT sensing fabric IPs has been validated on TSMC’s major processes ranging from 40nm to 5nm.
Moortec have been providing innovative embedded subsystem PVT IP solutions for over a decade, empowering their customers with the most advanced monitoring IP on 40nm, 28nm, 16nm, 12nm, 7nm and 5nm. Moortec’s in-chip sensing products support the semiconductor design community’s demands for increased device reliability and enhanced performance optimisation, helping to bring product success by differentiating the customers’ technology. With a world-class design team, excellent support and a rapidly expanding global customer base, Moortec are the go-to leaders in innovative in-chip technologies for the automotive, consumer, high performance computing, mobile and telecommunications market sectors.