Webinar: Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards

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Presenter: Krzysztof Szczur, Verification Products Manager
Thursday, October 10, 2019

Abstract:

Presently, emulation and FPGA-based prototyping are essential verification and validation techniques for a SoC, ASIC designs and become irreplaceable in pre-silicon verification of Deep Learning Accelerator designs. Challenges of the multi-FPGA design setup like partitioning, multiplexing limited I/O interconnections and mapping multiple clock domains across multiple devices may cause significant delays in prototype bring-up and verification schedule. Design partitioning tool that can be used with either off-the-shelf or custom made FPGA boards will automate the most tedious tasks and so significantly reduce the risk.

Aldec provides HES-DVM Proto toolbox with automatic design partitioning for multiple FPGAs including Xilinx Virtex-7 and UltraScale XCVU440. In this webinar we will demonstrate how to compile and partition an open source design of Deep Learning Accelerator into 6 FPGAs in 6 steps which are fully automated.

  • Multi-FPGA Design Prototyping Challenges
  • HES-DVM Proto Overview
  • Live demo - 6 steps / 30 minutes to partition DLA design
  • Conclusion
  • Q&A

Event Info

EU Session

 3:00 PM – 4:00 PM CEST

  Thursday, October 10, 2019

Register for EU Session

US Session

11:00 AM – 12:00 PM PDT

Thursday, October 10, 2019

Register for US Session

Presenter

 Krzysztof Szczur

Bio:

(Chris) Krzysztof Szczur is a Hardware Verification Products Manager at Aldec.

Chris joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based emulation and prototyping technology. In his engineering career he has also worked in the fields of HDL design verification, testbench automation and DO-254 compliance. Krzysztof has practical experience and a deep understanding of hardware assisted verification methodologies. Krzysztof graduated as M.Eng. in Electronic Engineering (EE) at the AGH University of Science and Technology in Krakow, Poland.

 




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