Imperas developed compliance tests quantified by open source collaboration of verification coverage tools developed by Google Cloud
Oxford, United Kingdom, November 26, 2019 — Imperas Software Ltd. , the leader in virtual platforms and high-performance software simulation, today announced the release of the latest update to the RISC-V compliance test suite for RV32I base RISC-V configuration. Developed in conjunction with the RISC-V Foundation's Technical Committee task group for compliance, Imperas has achieved an almost 100% functional coverage of the instructions in the RISC-V ISA base specification known as RV32I.
Imperas has uploaded the updated RV32I compliance suite to the RISC-V Foundation GitHub repository for the compliance task group, available at https://github.com/riscv/riscv-compliance.
In addition, Imperas has also updated the free RISC-V Open Virtual Platform Simulator (riscvOVPsim™) as a reference Instruction Set Simulator (ISS) for users and developers of the compliance suite, which is available on GitHub at https://github.com/riscv/riscv-ovpsim.
"As an open ISA, the RISC-V task groups are facing many challenges not currently addressed by the mainstream tools available within the industry,” said Allen Baum of Esperanto Technologies, Inc., who chairs the RISC-V Foundation's Technical Committee task group for compliance. “The team at Imperas has not just updated the base RV32I tests to an industry leading standard but has also established the framework for coverage and quality as we continue working to develop tests for the optional extensions.”
“Verification is important for any processor implementation but the RISC-V compliance tests need to ensure a level of interoperability across the entire ecosystem that the industry will depend on,” said Lee Moore, Sr. Consultant and lead compliance engineer, at Imperas Software Ltd. “Working closely with the Google Cloud team on the ISG project, we realized the same coverage methods could confirm the quality of the compliance suite, and thus help to both define and then close the gaps to make this RV32I update a complete and exhaustive test suite.”
“The RISC-V Foundation was formed to establish industry wide partnerships for innovation and collaboration focused on accelerating the support and adoption of RISC-V,” said Calista Redmond, CEO of the RISC-V Foundation. “The contributions by Imperas to the key RV32I compliance suite illustrates the dedication and expertise that is helping to ensure an ecosystem of compatibility that all members and users can build on.”
riscvOVPsim is free and available to download on GitHub as part of the latest RISC-V compliance test suite and framework at https://github.com/riscv/riscv-compliance. riscvOVPsim includes a free to use license from Imperas, which supports commercial as well as academic use. The open source RISC-V model is licensed under the Apache 2.0 license.
Availability: The free riscvOVPsim updates are available now on GitHub.
Imperas will present a technical paper on the work to develop and extend the compliance suite and latest verification techniques at the RISC-V Summit, in San Jose December 10-12, 2019. An additional Tutorial session on verification will also explain the exhaustive coverage methodologies that include the implementation flexibility permitted within the Open ISA of RISC-V. For more information see this link.
The riscvOVPsim solution is an entry ramp for development, as well as a compliance testing tool. For developers of more advanced RISC-V designs, who need multi-core support and advanced debug, verification and analysis tools, Imperas also offers full-capability virtual platforms of some leading RISC-V platforms including the multi-core SiFive U540 and many others. Further details are available at www.imperas.com/riscv.
Imperas is revolutionizing the development of embedded software and systems and is the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full, heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.
About the RISC-V Foundation
For more information about RISC-V (pronounced “risk-five”), please see