Semico Forecasts Strong Growth for RISC-V

Semico forecasts strong growth for RISC-V, predicting the market will consume 62.4 billion RISC-V CPU cores by 2025

San Francisco – Nov. 25, 2019 – The  RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced that Semico Research’s new report “RISC-V Market Analysis: The New Kid on the Block” estimates that the market will consume a total of 62.4 billion RISC-V CPU cores by 2025, with the industrial sector forecasted to be the largest segment with 16.7 billion cores. Forecasting the compound annual growth rate (CAGR) for RISC-V CPU cores, Semico estimates that segments including the computer, consumer, communication, transportation and industrial markets will see a 146.2 percent CAGR on average between 2018 and 2025.

“Semico’s report is testament to the incredible growth potential of RISC-V for commercial adoption and implementations across a variety of industries,” said Calista Redmond, CEO of the RISC-V Foundation. “At the RISC-V Foundation we’re proud to be witnessing such an incredible transformation in CPU design as the market embraces open software and silicon.”

Semico surveyed a cross section of companies in the RISC-V ecosystem and the broad market to analyze the market potential for RISC-V CPU cores. As part of this research Semico evaluated 25 markets to develop a forecast for the penetration rate of RISC-V, along with the number of cores that would be implemented over time. The firm analyzed data for 25 applications within five major end markets – computer, consumer, communications, transportation and industrial – to develop a forecast for four product categories: advanced performance multicore SoCs, value multicore SoCs, basic SoCs and FPGAs.

President of Semico Research, Jim Feldhan, commented: “We were surprised and excited to see how companies of all sizes are designing RISC-V solutions for a wide variety of applications for various performance and volume requirements. Based on the already sizeable adoption of RISC-V, we forecast that the market will consume a total of 62.4 billion RISC-V cores by 2025, signaling that RISC-V is on the fast track to mainstream adoption.”

In its forecast of the CAGR for RISC-V CPU cores between 2018 and 2025, Semico estimates that the communication sector will see the largest CAGR due to the deployment of 5G and the multitude of products and applications that will be enabled with the adoption of 5G technology. Transportation is estimated to have the second-fastest CAGR due to the automotive industry’s growing focus on electrification and the increased adoption of CPU-based systems for safety, in-cabin experiences, driver assistance and wireless communications. Semico not only found that organizations are designing RISC-V solutions across a variety of performance and volume applications, but also that they are designing anywhere from one or two to more than 1000 cores in SoCs.

Semico’s “RISC-V Market Analysis: The New Kid on the Block” report will be available on Wednesday, Nov. 20, 2019. To purchase the report, please click on this  link.

To learn more about the free and open RISC-V ISA, please visit: To become a member of the RISC-V Foundation, please visit:

Supporting Resources

About RISC-V Foundation

RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 420 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.


Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700
Email Contact

Review Article Be the first to review this article

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
What’s on Tap from the ESD Alliance? Plenty! Read On …
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automating IP and SoC Development
SerDes Applications Design Engineer for Xilinx at San Jose, California
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
Principle Engineer (Analog-Mixed-Signal Implementation) for Global Foundaries at Santa Clara, California
Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California
SoC Physical Design Engineer for Qualcomm at Austin, Texas
Technical Product Manager- SISW-EDA 238452 for Siemens AG at Fremont, California
Upcoming Events
Simulation World at United States - Apr 20 - 21, 2021
Virtual ASMC 2021 at United States - May 10 - 12, 2021
DVCon China 2021 at Shanghai China - May 26, 2021
CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021
Verific: SystemVerilog & VHDL Parsers

© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise