SHA IP Core with native SHA2-256 HMAC support

DCD, IP Core provider and SoC design house from Poland, introduced its latest DSHA2-256 IP Core, which is a universal solution which efficiently accelerates SHA2-256 hash with native HMAC mode. This IP targets authenticity and data integrity verification in digital signature protocols and all aspects of secured communication. It’s worth to mention that due to its unique features, the DSHA2-256 IP Core might also be used in crypto currency computations acceleration.

Bytom, Poland January the 7th 2020. -- The DCD's DSHA2-256 is a universal solution which accelerates SHA2-256 hash function compliant with FIPS PUB 180-4. It computes message digest either in 256 and 224 bit modes. Allowed input message length is up to 264 - 1 bit. The core is fully configurable, which significantly reduces design time. – Native support of the SHA2-256 HMAC (keyed-Hash Message Authentication Code) is a… key – says Jacek Hanke, DCD’s CEO – this cryptographic function defined in RFC 2104 is a must in all kinds of secured communication.

The DSHA2-256 is suitable for authenticity and data integrity verification in digital signature protocols and all other communication where security is the key. It might also be used in crypto currency computations accelerating. DCD’s IP Core offers context swapping feature which is extremely useful in complex systems with a task’s preemption mechanism and software managed or custom HMAC scheme.

SHA2 is a family of cryptography secure one-way compression functions based on Merkle-Damgard structure, the 256 version sequentially process 512 bit input blocks during 64 rounds. From arbitrary length input message (maximum 264 - 1 bits) it produces fixed 256 or 224 bit length digest in a way that it is practically infeasible to invert it (get original message from its digest). Such property is called a one-way function.  Cryptographic security of SHA2-256 is assumed at 128 bit level (112 bit in case of SHA2-224) which makes it appropriate to use in security applications. Some of them need to prove knowledge or possession of some secret data while computing message digest. For such authentication purpose the HMAC function has been designed. It combines both secret key and cryptography secure hash function (like SHA2-256).

Key features:

  • FIPS PUB 180-4 compliant SHA2-256 function
  • RFC 2104 compliant HMAC mode native support
  • SHA2 224 and 256 bit modes support
  • Secure storage for precomputed HMAC keys
  • Hash/HMAC context swapping
  • Internal, automatic padding module
  • Binary message resolution support
  • Flexible data read/write modes
  • AMBA AHB, AXI4, APB interface ready
  • Software support:
    • Software driver with OpenSSL/MbedTLS interface ready
  • Applications
    • Digital signature
    • Data integrity
    • Key derivation
    • TLS/SSH/PGP IPsec communication

Applications

  • Digital signature
  • Data integrity
  • Key derivation
  • TLS/SSH/PGP IPsec communication

Deliverables

The list of deliverables consists of:

  • Source code:
    • VERILOG Source Code
    • Software driver in C with OpenSSL/MbedTLS interface ready
  • VERILOG test bench environment
    • Active-HDL automatic simulation macros
    • ModelSim automatic simulation macros
    • Tests with reference responses
  • Technical documentation
    • HDL core specification
    • Software driver documentation
  • Synthesis scripts
  • Example application
  • Technical support
    • IP Core implementation support
    • 3 months of maintenance
      • Delivery the IP Core updates, minor and major versions changes
      • Delivery the documentation updates




Contact:

Thomas Cwienk
PR Manager
+48 502 915 777
Email Contact
Skype: tomasz.cwienk




Review Article Be the first to review this article
Aldec

 Advanced Asembly

Featured Video
Latest Blog Posts
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automating IP and SoC Development
Jobs
Business Operations Planner for Global Foundaries at Santa Clara, California
Circuit Design & Layout Simulation Engineer - Co-Op (Spring 2021) for Global Foundaries at Santa Clara, California
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
SerDes Applications Design Engineer for Xilinx at San Jose, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
ASIC SoC Verification Engineer for Ericsson at Austin, Texas
Upcoming Events
Virtual ASMC 2021 at United States - May 10 - 12, 2021
DVCon China 2021 at Shanghai China - May 26, 2021
CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021
DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021
True Circuits PHY



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise