Aldec and Codasip at Embedded World: Showcasing an Integrated UVM Simulation Environment for Verifying Custom Instructions with RISC-V Cores

NUREMBERG, Germany — (BUSINESS WIRE) — February 19, 2020 — Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, is exhibiting at Embedded World in Nuremberg, Germany on February 25-27, 2020. Aldec and Codasip will be showcasing an integrated UVM simulation environment for verifying custom instructions with RISC-V cores.

By integrating Aldec’s Riviera-PRO™ with Codasip’s Studio™, verification of custom instructions at the RTL implementation level becomes an incredibly powerful platform for RISC-V processor deployment.

  • In Studio, users can
    • describe the RISC-V architecture and add custom instructions using CodAL high level language
    • modify the pipeline
    • configure random instruction generator
    • auto-generate the HDK, SDK, RTL implementation and C++ reference model and UVM environment
    • start RTL simulation
    • setup breakpoints
    • debug
  • In Riviera-PRO, users can
    • run RTL simulation and debug applications and core architecture
    • inspect simulation waveforms
    • use the UVM Graph & Toolbox to view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections between them giving the user an overall perspective on the testbench architecture and the dataflow
    • use code coverage to analyse the efficiency of the UVM tests for exercising various parts of the RTL implementation code

“The ability to add custom instructions to processor IPs is a remarkable advantage of the open-source RISC-V ISA,” said Louie De Luna, Aldec’s Director of Marketing. “Custom instructions lead to higher performance with less amount of code, and useful for optimizing the core for targeting specific embedded applications. We look forward to continue to work with Codasip as we address new verification challenges with RISC-V.”

“Variability of the RISC-V ISA-based processor family brings new challenges to design flow. In particular, IP and SoC verification needs productivity boost tools and seamless integration into our design environment,” said Karel Masařík, CEO of Codasip. “Our generic UVM methodology combined with Aldec's simulation and code coverage efficiency analysis helps us add the desired RISC-V core extensions and provide core customization faster than our competition.”

See the demo and talk to our experts at Aldec Booth#4-560 and Codasip Booth#3A-536 (RISC-V booth, pod 13).

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification. Established in 1984, Aldec offers patented technology in the areas of mixed-language RTL simulation, FPGA acceleration and emulation, SoC/ASIC prototyping, design rule checking, clock domain crossing analysis, requirements traceability and functional verification for military, aerospace, avionics, automotive and industrial applications. www.aldec.com

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. www.codasip.com

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.



Contact:

Richard Warrilow
Declaration Limited
T: +44 (0)1522 789 000
richardw@aldec.com




Review Article Be the first to review this article
Aldec

New Customer Special

Featured Video
Jobs
Senior and (less) Senior Design Verification Engineers for EDA Careers at San Jose and Austin, California
Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Sr. Principal FPGA for Northrop Grumman Mission Systems at Morrisville, North Carolina
Staff Engineer Digital-20003075 for Northrop Grumman Mission Systems at Redondo Beach, California
Principal Electronics Engineer Test-20004966 for Northrop Grumman Mission Systems at Falls Church,, Virginia
Upcoming Events
Embedded Vision Summit 2020 at Santa Clara Convention Center Santa Clara CA - May 18 - 21, 2020
Sensors Expo & Conference at McEnery Convention Center 150 W. San Carlos Street SAN JOSE CA - Jun 22 - 24, 2020
Nanotech 2020 Conference and Expo at National Harbor MD - Jun 29 - 1, 2020
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise