The new PHY VIP enables comprehensive and fast verification of the physical layer for complex protocols such as PCIe 5.0, USB3/4, DDR5, LPDDR5, HBM and MIPI CSI-2 and DSI 2.0
SAN JOSE, Calif. — (BUSINESS WIRE) — February 26, 2020 — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the availability of the industry’s first Verification IP (VIP) for physical layer (PHY) verification. The Cadence® VIP for PHY covers multiple protocols and allows customers to thoroughly test and optimize their PHY designs, accelerating the development of data center, artificial intelligence (AI), machine learning (ML) and mobile application designs.
The Verification IP for PHY is part of the Cadence Verification Suite™ and supports the company’s Intelligent System Design™ strategy, enabling SoC design excellence through best-in-class IP. For more information on the Cadence PHY VIP, please visit www.cadence.com/go/PHYVIP.
The new Cadence VIP for PHY offers customers a comprehensive verification solution for the most complicated and challenging physical-layer interfaces and protocols, including PIPE 5.2 for PCI Express® (PCIe®) 5.0, USB3 and USB4, DFI for LPDDR4, DDR5 and HBM2E, and MIPI® D-PHY�nbsp;/C-PHY�nbsp; for CSI-2�nbsp; 2.0 and DSI�nbsp; 2.0. With the PHY VIP, customers can shorten time to market through advanced built-in capabilities for PHY verification such as:
- PHY-level timing checks
- Ability to drive protocol-aware and protocol-agnostic traffic for exhaustive testing
- A built-in scoreboard for analyzing receive path, transmit path and loopback
- Control over jitter, spread spectrum clock and bit error rate
Additionally, the solution includes Cadence TripleCheck™ technology, which provides users with a PHY-related verification plan that is linked to the specification as well as comprehensive coverage models and a test suite to ensure compliance with the interface specification.
“Our PHY team has successfully utilized Cadence VIP for verification of various protocols such as USB3 and PCIe 4.0, enabling us to quickly deliver unique and innovative designs for a broad range of applications,” said Realtek’s Vice President and Spokesman, Yee-Wei Huang. “With the complexity inherent in verifying PHY designs, Cadence VIP for PHY addresses a critical and challenging verification task and provides the speed and accuracy we need to help our customer’s time to market.”
“PHY verification requires unique methods to ensure that all timing, power and throughput requirements are met in various conditions,” said Moshik Rubin, Verification IP product management group director, System and Verification Group at Cadence. “With the industry’s first dedicated VIP for PHY, we’re enabling our customers to verify their PHY designs effectively, ensuring the designs comply with the standard specification and meet application-specific performance metrics to provider the fastest path to IP verification closure.”
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.
© 2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. PCI Express and PCIe are registered trademarks or trademarks of PCI-SIG. MIPI, C-PHY, CSI-2, D-PHY, and DSI are registered trademarks or service marks owned by MIPI Alliance. All other trademarks are the property of their respective owners.