Imperas announce first reference model with UVM encapsulation for RISC-V verification

Imperas RISC-V reference models now available with SystemVerilog UVM side-by-side step and compare verification testbenches for RTL processor cores in leading commercial Design Verification (DV) environments

Oxford, United Kingdom, February 2 4th , 2020 —  Imperas Software Ltd. the leader in virtual platforms and high-performance software simulation, today announced the latest enhancements to its range of RISC-V reference models and solutions to support processor verification, with the leading commercial SystemVerilog hardware design verification environments provided by Cadence, Mentor, Synopsys, and also the Metrics cloud based tools. Working together with lead customers, industry groups and associations, and the Google Instruction Stream Generator (ISG) developers, Imperas has enhanced the OVPsim reference models to support the comparison with directed tests, the RISC-V Foundation’s compliance tests, and tests created by the open source Google random ISG. The new approach to encapsulate the reference models within a SystemVerilog UVM (Universal Verification Methodology) test bench to allows a side-by-side comparison (step and compare verification) of RTL and reference model within the same environment for an interactive transaction-based analysis. 

With this new release, hardware developers can for the first time use a golden reference model of a RISC-V processor alongside their RTL in their SystemVerilog UVM design verification (DV) environments.

The traditional view of the SoC design flow typically estimates that between 40% to 70% of the time and effort is directed at verification tasks. Based on the assumption of “known-good” semiconductor IP cores, the SoC verification is focused almost completely on the unique value-added features outside of the cores. Now with RISC-V, SoC developers can enjoy the additional design freedoms of an open ISA and explore options for customized, optimized instructions and extensions. In addition, the latest many-core SoCs can now utilize a broad range of individually optimized cores, each tailored to the rightsize requirements. Verification at the RISC-V core level is now an essential task for any SoC design with a custom processor, or custom instructions.

All processor developers need a full and detailed hardware verification environment although for many years the ISA and processor developers inside well-respected industry firms have built their own proprietary DV solutions and flows. It is only with RISC-V that there is a need for the industry as a whole to have access to technologies that were traditionally proprietary and closed environments. This new Imperas release is the beginning of a hardware verification environment being made generally available to the wider community of designers, developers and DV engineers.

The simulation components of a complete DV test plan are based on 4 essential elements: the Device Under Test (DUT) RTL, the test framework, the quality reference model, and suitable tests to compare against. In addition to working with the Google ISG, Imperas has also contributed to the RISC-V Foundation working group on compliance, including the development of the latest RV32 test suites. For the RISC-V Vector extensions, Imperas has developed a new Vector compliance suite, and a directed test suite based on the latest draft specification. To support lead customers, these enhanced features and tests are being provided as an upgrade to the current Imperas commercial products and are already in active use.

"The driving requirement for the RISC-V ISA was the freedom to allow implementors the greatest possible flexibility while retaining the efficiencies and advantages of a common base framework,” said  Krste Asanovic, SiFive Chief Architect and Chairman of the RISC-V Foundation.  "With a growing base of RISC-V implementors, not only academic and research projects but also increasingly for production deployments that demand extensive verification, it is exciting to see Imperas providing an essential link to the traditional and established commercial SoC verification communities.”

"The OpenHW Group is focused on the delivery of open source cores for use in high volume SoCs that have been verified to a level of quality normally associated with commercial IP providers,” said  Rick O'Connor, President and CEO, OpenHW Group. “To illustrate the rigor and quality of the cores we will also open-source the verification flows and documentation, and now with the UVM encapsulation of the Imperas RISC-V reference model we can fully support all the standard SystemVerilog tool environments our users expect.”

"As chair of the Compliance working group, I have been fortunate to meet with many implementers across the RISC-V community and industry,” said  Allen Baum of Esperanto Technologies, Inc., who chairs the RISC-V Foundation's Technical Committee task group for compliance. “While they are all interested in the compliance work, the recurring question is how do experienced SoC test and verification teams start a processor DV project? Imperas's reference model with UVM encapsulation provides an excellent, useful starting place for this work.”

“Having been closely involved with SystemVerilog from the very start, and followed the adoption by the DV community in developing sophisticated UVM flows, I can see how fundamental this has become to modern designs,” said  Simon Davidmann, CEO at Imperas Software Ltd. “The verification that is required for a design to achieve the quality metrics for a tape-out release is significant. Now with Imperas technology and reference models being available in the trusted SystemVerilog UVM environments that the industry depends on, the DV teams can address the coming wave of RISC-V innovation.”

Availability: The UVM encapsulation of the Imperas RISC-V reference model, testbench examples, application notes and documentation are available now for evaluation:  visit or

Imperas will present a technical paper on the RISC-V verification work with the Google open-source ISG titled “Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification” at DVCon 2020, in San Jose March 2-5. An additional panel session on verification will cover the latest views on the disruption and challenges currently facing the industry today. For more information visit  Imperas at DVCon2020.

Imperas also provides the riscvOVPsim solution as a free resource on GitHub, as an entry ramp for development, as well as a compliance testing tool. For developers of more advanced RISC-V designs, who need multi-core support and advanced debug, verification and analysis tools, Imperas also offers full-capability virtual platforms of some leading RISC-V platforms including the multi-core SiFive U540 and many others. 

Further details are available at

About Imperas

Imperas is revolutionizing the development of embedded software and systems and is  the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux.  All models are available from Imperas at  and the  Open Virtual Platforms (OVP)  website.

For more information about Imperas, please see Follow Imperas on  LinkedIntwitter @ImperasSoftware and  YouTube.

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