LOUISVILLE, Colo., March 12, 2020 (GLOBE NEWSWIRE) -- The 2020 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded its 32nd annual event last week. The 2020 Best Paper and Poster winners, as voted on by attendees, were announced at the closing reception.
The Steering Committee adjusted the conference and exhibition schedule to three days from the traditional four-day program to accommodate schedule changes. To honor the work that all session, tutorial, poster, short workshop, panel presenters and exposition partners put into the conference, and to connect with registered attendees who were unable to participate in person, the DVCon U.S. Steering Committee is exploring plans for an online experience, details of which will be announced later.
“I’d like to congratulate all of our paper and poster winners this year,” stated Vanessa Cooper, DVCon U.S. Technical Program Committee Chair. "There were many quality papers presented so attendees were once again treated to excellent content. I'm excited that we get to continue the program through a virtual offering with the presentations that were not able to be represented. I’d also like to thank those who were able to fill in program gaps as it serves to highlight the quality of our attendees and their depth of knowledge, which DVCon U.S. has come to depend on and respect.”
The award for the Stuart Sutherland Best Paper Presentation, as voted by conference attendees, went to: Heath Chambers, HMC Design Verification, Inc. & Sunburst Design, Inc.; Clifford E. Cummings, Sunburst Design, Inc. and Stephen D’Onofrio, Paradigm Works, Inc. & Sunburst Design, Inc. for their paper, “UVM Reactive Stimulus Technique.” Second place was awarded to: Chris Spear and Rich Edelman, Mentor, A Siemens Business, for their paper, “UVM – Stop Hitting Your Brother Coding Guidelines.” Gabriel Jönsson and Lars Viklund of Axis Communications AB took third place honors for their paper, “A SystemVerilog Framework for Efficient Randomization of Images with Complex Inter-Pixel Dependencies.”
Top honors for Best Poster went to Kubendra Kumbar and Ken Joseph Kannampuzha, Samsung Semiconductor India R&D, Bangalore; Sandeep Vallabhanen, Shim Hojun and Byung C. Yoo, Samsung Electronics Co., Ltd. for their poster, “SoC Firmware Debugging Tracer in Emulation Platform.” Second place was awarded to Mark Eslinger, Jeremy Levitt and Joe Hupcey III, Mentor, A Siemens Business for their poster, “Deadlock Verification for Dummies - The Easy Way Using SVA and Formal.” Third place was awarded to Brandon Skaggs, Cypress Semiconductor Corp. for his poster, “Addressing the Challenges of Generically Specifying Power Intent with Multi-Rail Macros.”
New to DVCon this year was the ability for attendees to track the conference schedule and communicate with each other through the Whova App. The app proved invaluable to keep attendees up to date as the schedule was adjusted to accommodate last-minute alterations to the program. Attendees were also able to vote for their selections for Best Paper and Best Poster through the app.
Highlights of the Week:
- The conference hit the ground running on Monday with Accellera Day featuring a full morning tutorial on the upcoming new version of the Portable Test and Stimulus Standard (PSS).
- The Accellera-sponsored luncheon began with the presentation of the Accellera 2020 Technical Excellence Award. Philipp A. Hartmann was honored for his contributions to the advancement of the SystemC language standard. Most recently, Hartmann was Chair of the SystemC Language Working Group. He has been an active member of Accellera for many years, driving the evolution of the SystemC standard as well as being one of the most crucial contributors to the code development of the SystemC reference implementation.
- The Monday luncheon continued with a lively panel discussion on PSS which gave the audience a chance to interact with members of the Portable Stimulus Working Group to find out more about the process behind the development of this exciting new standard.
- The panel on Tuesday, “New Chip Designs Create Tidal Wave of Change” provided a town hall discussion for attendees on the need for a more thorough verification methodology as complexity converges with open source initiatives such as RISC-V. The panel covered everything from methodologies to start up opportunities, and provided insight from users, vendors and Jim Hogan, a leading EDA investor.
- Short workshops continued to be well-received by attendees this year. The workshops give attendees an opportunity to learn from a broader set of vendors, including smaller companies. This year there were eight short workshops to choose from.
Accellera’s sponsored tutorial and short workshops will be available online shortly. An announcement will be made when they are posted to its website for public access.
The DVCon Steering Committee values all feedback regarding the conference. DVCon U.S. attendees have been given a survey and are asked to provide input and feedback on how we can improve and continue to make DVCon the industry’s must-attend conference for design and verification engineers.
Save the date: DVCon U.S. 2021 will be held March 1-4 at the DoubleTree Hotel in San Jose, California.
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DVCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.
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