Mixel’s MIPI D-PHY IP Integrated into the Lattice CrossLink-NX FPGA

World’s first low-power FPGA to support D-PHY v1.2 with 2.5Gbps/lane

SAN JOSE, Calif. — (BUSINESS WIRE) — April 28, 2020Mixel®, a leading provider of mixed-signal intellectual property (IP), announced today that Mixel’s MIPI® IP solution has been successfully integrated into Lattice Semiconductor’s Crosslink-NXTM FPGA now sampling to customers.

Built using the new 28 nm FD-SOI Lattice Nexus™ FPGA platform, the CrossLink-NX FPGAs outperform FPGAs of similar class in terms of power, form factor, reliability, and performance. The CrossLink-NX FPGAs were developed for use in applications including sensor and display bridging, sensor aggregation, sensor duplication, and AI inferencing at the Edge.

The MIPI D-PHYSM link can operate between 1 to 4 lanes and supports an aggregated data rate of 10 Gbps per instance. The Mixel IP incorporates proprietary differentiating features to reduce stand-by current and wake-up time.

Mixel provided Lattice with the MIPI D-PHY Universal IP that supports both the transmit and receive functionality for both MIPI CSI-2SM and MIPI DSISM applications. CrossLink-NX is the second product that Lattice has integrated Mixel’s MIPI IP. An earlier generation of the Mixel D-PHY Universal IP was integrated into the CrossLink Programmable ASSP™, an earlier member of the CrossLink family. In both products, Lattice achieved first-time silicon success.

“When it came to vendor selection, we trusted Mixel to provide a high-quality differentiated IP that worked the first time,” said Gordon Hands, Director of Product Marketing, Lattice Semiconductor. “Choosing Mixel’s MIPI IP for our new CrossLink-NX family of FPGAs is a testament to our long-term partnership with Mixel and their commitment to our success.”

Both generations of the Lattice CrossLink products were the first of their kind to support MIPI PHY interfaces at their respective level of speed, both integrating Mixel IP.

Mixel MIPI IP has been silicon-proven at nine different nodes and eight different foundries with more processes under active development, giving Mixel the widest coverage in the industry.

“We are proud to deliver yet another D-PHY IP with first-time silicon success to Lattice Semiconductors, a longtime Mixel customer and partner,” said Ashraf Takla, Mixel’s President and CEO. “We are also delighted to be part of the world’s first low-power FPGA to support advanced MIPI capabilities, again!”

About Mixel:

Mixel is a leading provider of mixed-signal IPs and offers a wide portfolio of high-performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes, such as MIPI D-PHYSM, MIPI M-PHY®, MIPI C-PHYSM, LVDS, and many dual mode PHY supporting multiple standards. Mixel was founded in 1998 and is headquartered in San Jose, CA, with global operation to support a worldwide customer base. For more information contact Mixel at info@mixel.com or visit www.mixel.com. You can also follow Mixel on LinkedIn, Twitter, Facebook, or YouTube.

About MIPI Alliance:

MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. There is at least one MIPI specification in every smartphone manufactured today. Founded in 2003, the organization has over 300 member companies worldwide and 14 active working groups delivering specifications within the mobile ecosystem. Members of the organization include handset manufacturers, device OEMs, software providers, semiconductor companies, application processor developers, IP tool providers, automotive OEMs and Tier 1 suppliers, test and test equipment companies, as well as camera, tablet and laptop manufacturers. For more information, please visit www.mipi.org.

Mixel® and the Mixel logo are registered trademarks of Mixel, Inc.

MIPI® and MIPI M-PHY® are registered trademarks owned by MIPI Alliance. MIPI CSI-2SM, MIPI C-PHYSM, MIPI D-PHYSM and MIPI DSISM are service marks of MIPI Alliance.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.



Contact:

Mixel, Inc.
Justin Endo
(408) 436-8500 x117
Email Contact
www.mixel.com




Review Article Be the first to review this article
Aldec

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automation of the UVM Register Abstraction Layer
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Virtual 2020 CEO Outlook Set for June 17
Colin WallsEmbedded Software
by Colin Walls
Multiple constructors in C++
Jobs
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Software Engineer for EDA Careers at RTP, North Carolina
Upcoming Events
Sensors Expo & Conference at McEnery Convention Center 150 W. San Carlos Street SAN JOSE CA - Jun 22 - 24, 2020
Nanotech 2020 Conference and Expo at National Harbor MD - Jun 29 - 1, 2020
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise