SUNNYVALE, Calif., June 09, 2020 (GLOBE NEWSWIRE) -- Real Intent, Inc., today announced
Verix DFT, a full-chip, multimode DFT static sign-off tool. Verix DFT’s comprehensive set of fine-grained DFT rules help designers to rapidly identify design violations and improve scan testability and coverage.
Verix DFT is deployed throughout the design process: 1) during RTL design, as part of addressing asynchronous set/reset, clock and connectivity issues early, 2) after scan synthesis, to check for scan chain rule compliance, and 3) following place & route to assess and correct issues with scan-chain reordering or netlist modification.
Multimode Reduces DFT Static Sign-off by Weeks
Verix Multimode DFT can reduce static sign-off time by several weeks. The savings are gained from lower setup time, runtime speedup, and the reduced engineering debug and violation fixing due to consolidated reporting.
In a single run, the tool can analyze:
- Multiple ATPG partitions, eliminating the time-consuming process of running DFT static sign-off for each partition separately
- Multiple constraint sets, where each constraint set corresponds to the ATPG pattern type
- Multiple constraint sets across multiple test modes
“Running DFT static sign-off repeatedly to verify each ATPG partition and each constraint set is extremely time consuming,” said Prakash Narain, President and CEO of Real Intent.
Narain continued, “Additionally, much of design for testability analysis today occurs late in the cycle, when it is far more expensive to find and fix errors. Real Intent Verix DFT’s multimode design for testability static sign-off can be used early and at different design stages to reduce DFT static sign-off time by weeks and improve scan testability and coverage.”
Robust coverage, Fine-grained rules, and Root Cause Analysis
Verix DFT’s unique characteristics enable designers to prepare their RTL and gate-level designs for the highest possible quality ATPG pattern generation and silicon success.
In addition to its multimode analysis capability, Verix DFT has:
- Capacity/Performance. Verix DFT can handle multimillion-gate designs in minutes, with full chip capacity and a low peak memory footprint.
- High Coverage Rule Sets. Real Intent uses the industry’s most comprehensive array of rules to help ensure high coverage at all design stages, including asynchronous set/reset, clock, scan-chain, flip-flop, port & connectivity signoff rules, and a variety of basic setup checks.
- Fine-grained rules. The fine-grained rules enable faster identification of specific design fixes.
- Rule Selection & Configurability by Test Mode. Verix DFT’s rules can be selectively enabled in every test mode, such that the different test modes can each have different rules enabled. The severity level (error, warning, or information) is also configurable by test mode.
- Fast Setup. Verix DFT is easy to set up and use, requiring only a few hours, rather than the weeks required with other DFT static tools.
- Smart, tiered violation reports. The tool’s accurate, detailed design analysis delivers more precise reporting, without duplicating violations. Verix DFT’s violation reporting lets you hierarchically categorize the violations, and then toggle to expand or collapse the violations groups. The violations are organized in a tiered priority order, providing guidance to help designers more quickly pinpoint the root cause problems.
- Integrated iDebug. As with all Real Intent static sign-off tools, Real Intent has integrated its iDebug debugging platform to provide schematics to facilitate DFT check debugging, with cross-probing and easy waivers that can be ported between runs.
- Root-cause analysis & recommended fixes. Verix DFT labels schematics with rule-specific debug information, such as the glitch sources and the convergence instances for reset glitch rules. The complete debug path is shown for path-based rule violations. Additionally, the tool provides precise user instructions on set up changes required to fix specific violations.
Fault Coverage Estimation Option
Verix DFT has an additional tool option for fault coverage estimation. When the option is enabled, it will provide fault coverage for each test-mode, along with a rollup of overall scan test fault coverage estimation.
By automatically estimating the fault coverage for each test mode, the user can better prioritize violation debug order and assess readiness for sign-off.
For more information on Verix Multimode DFT, please visit: https://www.realintent.com/design-for-testability-verix-multimode-dft/
About Real Intent
Real Intent provides intent-driven static sign-off EDA software tools to accelerate early functional verification and advanced sign-off of digital designs. Its product capabilities include: clock domain crossing sign off from RTL through gate level -- including multimode CDC; reset domain crossing sign off; multimode DFT sign-off; and both RTL linting and formal linting. Real Intent products lead the market in precision, performance, and capacity. Real Intent customers include more than 50 major semiconductor and systems companies. Real Intent is headquartered at 932 Hamlin Court, Sunnyvale, CA. For more information visit us at www.realintent.com.
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